82P2821BH IDT, Integrated Device Technology Inc, 82P2821BH Datasheet - Page 9

• Manufacturer Part Number: 82P2821BH
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2821BH

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

IDT82P2821
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Figure-49 JTAG Architecture ..................................................................................................................................................................................... 118
Figure-50 JTAG State Diagram ................................................................................................................................................................................. 119
Figure-51 Transmit Clock Timing Diagram ................................................................................................................................................................ 131
Figure-52 Receive Clock Timing Diagram ................................................................................................................................................................. 131
Figure-53 CLKE1 Clock Timing Diagram ................................................................................................................................................................... 132
Figure-54 E1 Jitter Tolerance Performance ............................................................................................................................................................... 134
Figure-55 T1/J1 Jitter Tolerance Performance .......................................................................................................................................................... 134
Figure-56 E1 Jitter Transfer Performance ................................................................................................................................................................. 135
Figure-57 T1/J1 Jitter Transfer Performance ............................................................................................................................................................. 135
Figure-58 Read Operation in Serial Microprocessor Interface .................................................................................................................................. 136
Figure-59 Write Operation in Serial Microprocessor Interface ................................................................................................................................... 136
Figure-60 Timing Diagram ......................................................................................................................................................................................... 137
Figure-61 Parallel Motorola Non-Multiplexed Microprocessor Interface Read Cycle ................................................................................................ 138
Figure-62 Parallel Motorola Non-Multiplexed Microprocessor Interface Write Cycle ................................................................................................ 139
Figure-63 Parallel Intel Non-Multiplexed Microprocessor Interface Read Cycle ....................................................................................................... 140
Figure-64 Parallel Intel Non-Multiplexed Microprocessor Interface Write Cycle ........................................................................................................ 141
Figure-65 Parallel Motorola Multiplexed Microprocessor Interface Read Cycle ........................................................................................................ 142
Figure-66 Parallel Motorola Multiplexed Microprocessor Interface Write Cycle ........................................................................................................ 143
Figure-67 Parallel Intel Multiplexed Microprocessor Interface Read Cycle ............................................................................................................... 144
Figure-68 Parallel Intel Multiplexed Microprocessor Interface Write Cycle ............................................................................................................... 145
Figure-69 JTAG Timing ............................................................................................................................................................................................. 146
List of Figures
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February 6, 2009