82P2821BH IDT, Integrated Device Technology Inc, 82P2821BH Datasheet - Page 24

• Manufacturer Part Number: 82P2821BH
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2821BH

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Pin Description
IDT82P2821
INT/MOT
TEHWE
GPIO[0]
GPIO[1]
TEHW
Name
RST
INT
P/S
OE
CS
Output / Input
(Pull-Up)
(Pull-Up)
(Pull-Up)
Output
Input
Input
Input
Input
Input
Input
Input
I / O
Pin No.
AG10
AG16
AF12
AF10
AK16
AF14
AJ10
AF11
AJ17
AF9
OE: Output Enable
OE enables or disables all Line Drivers globally.
A high level on this pin enables all Line Drivers while a low level on this pin places all Line
Drivers in High-Z state and independent from related register settings.
Note that the functionality of the internal circuit is not affected by OE.
If this pin is not used, it should be tied to VDDIO.
This pin can be used to control the transmit impedance state for Hitless protection applica-
tions. Refer to Section 4.4 Hitless Protection Switching (HPS) Summary for details.
TEHWE: Hardware T1/J1 or E1 Mode Selection Enable
When this pin is open, the T1/J1 or E1 operation mode is selected by TEHW globally.
When this pin is low, the T1/J1 or E1 operation mode is selected by the T1E1 bit (b0,
CHCF,...) on a per-channel basis.
TEHW: Hardware T1/J1 or E1 Mode Selection
When TEHWE is open, this pin selects the T1/J1 or E1 operation mode globally:
Low - E1 mode;
Open - T1/J1 mode.
When TEHWE is low, the input on this pin is ignored.
GPIO: General Purpose I/O [1:0]
These two pins can be defined as input pins or output pins by the DIR[1:0] bits (b1~0, GPIO)
respectively.
When the pins are input, their polarities are indicated by the LEVEL[1:0] bits (b3~2, GPIO)
respectively.
When the pins are output, their polarities are controlled by the LEVEL[1:0] bits (b3~2, GPIO)
respectively.
RST: Reset (Active Low)
A low pulse on this pin resets the device. This hardware reset process completes in 2 µs max-
imum. Refer to Section 4.1 Reset for an overview on reset options.
INT: Interrupt Request
This pin indicates interrupt requests for all unmasked interrupt sources.
The output characteristics (open drain or push-pull internally) and the active level are deter-
mined by the INT_PIN[1:0] bits (b3~2, GCF).
CS: Chip Select (Active Low)
This pin must be asserted low to enable the microprocessor interface.
A transition from high to low must occur on this pin for each Read/Write operation and CS
should remain low until the operation is over.
P/S: Parallel or Serial Microprocessor Interface Select
P/S selects Serial or Parallel microprocessor interface for the device:
GNDD - Serial microprocessor interface.
VDDIO - Parallel microprocessor interface.
Serial microprocessor interface consists of the CS, SCLK, SDI, SDO pins.
Parallel microprocessor interface consists of the CS, INT/MOT, IM, DS/RD, ALE/AS, R/W/WR,
ACK/RDY, D[7:0], A[10:0] pins.
INT/MOT: Intel or Motorola Microprocessor Interface Select
In Parallel microprocessor interface, INT/MOT selects Intel or Motorola microprocessor inter-
face for the device:
GNDD - Parallel Motorola microprocessor interface.
Open - Parallel Intel microprocessor interface.
In Serial microprocessor interface, this pin should be left open.
MCU Interface
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
24
Description
February 6, 2009