82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 14

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-4 Active Clock Edge and Active Level
Table-3 System Interface Configuration (In Host Mode)
2.3
high, the active edge of RCLKn is the rising edge, as for SCLK, that is
falling edge. On the contrary, if CLKE is low, the active edge of RCLK is
the falling edge and that of SCLK is rising edge. Pins RDn/RDPn, CVn/
RDNn and SDO are always active high, and those output signals are
clocked out on the active edge of RCLKn and SCLK respectively. See
Table-4 Active Clock Edge and Active Level on page 14
However, in dual rail mode without clock recovery, pin CLKE is used to
set the active level for RDPn/RDNn raw slicing output: High for active
high polarity and low for active low. It should be noted that data on pin
SDI are always active high and are sampled on the rising edges of
SCLK. The data on pin TDn/TDPn or BPVIn/TDNn are also always
active high but is sampled on the falling edges of TCLK, despite the level
on CLKE.
2.4
transformer and are converted into RZ digital pulses by a data slicer.
Adaptation for attenuation is achieved using an integral peak detector
that sets the slicing levels. Clock and data are recovered from the
received RZ digital pulses by a digital phase-locked loop that provides
jitter accommodation. After passing through the selectable jitter attenu-
ator, the recovered data are decoded using B8ZS/HDB3 or AMI line
code rules and clocked out of pin RDn in single rail mode, or presented
on RDPn/RDNn in an undecoded dual rail NRZ format. Loss of signal,
alarm indication signal, line code violation and excessive zeros are
detected. The presence of programmable inband loopback codes are
also detected. These various changes in status may be enabled to
generate interrupts.
2.4.1
pulses. In data recovery mode, the raw positive slicer output appears on
RDPn while the negative slicer output appears on RDNn. In clock and
IDT82V2044
Pin MCLK
Functional Description
The active edge of RCLKn and SCLK are selectable. If pin CLKE is
In receive path, the line signals couple into RRINGn and RTIPn via a
The slicer determines the presence and polarity of the received
Clocked
Clocked
Clocked
Clocked
Pin CLKE
High
Low
High
Low
CLOCK EDGES
RECEIVER
PEAK DETECTOR AND SLICER
Pin TDNn
Pulse
Pulse
Pulse
Pulse
Pulse
High
RCLKn
RCLKn
CRSn in e-CRS
Clock Recovery
Pin RDn/RDPn and CVn/RDNn
0
0
0
1
-
-
Active High
Active High
SINGn in e-SING
0
1
0
0
-
-
for details.
Slicer Output
Active High
Active Low
Single Rail Mode 1
Single Rail Mode 2
Dual Rail mode with Clock Recovery
Dual Rail mode with Data Recovery
Receive just slices the incoming data. Transmit is determined by the status of TCLKn.
Receiver n is powered down. Transmit is determined by the status of TCLKn.
14
data recovery mode, the slicer output is sent to Clock and Data
Recovery circuit for abstracting retimed data and optional decoding. The
slicer circuit has a built-in peak detector from which the slicing threshold
is derived. The slicing threshold is default to 50% (typical) of the peak
value.
ered by the receiver. To provide immunity from impulsive noise, the peak
detectors are held above a minimum level of 0.150 V typically, despite
the received signal level.
2.4.2
Locked Loop (DPLL). The DPLL is clocked 16 times of the received
clock rate, i.e. 24.704 MHz in T1 mode or 32.768 MHz in E1 mode. The
recovered data and clock from DPLL is then sent to the selectable Jitter
Attenuator or decoder for further processing.
channel basis by setting bit CRSn in register e-CRS. When bit CRSn is
defaulted to ‘0’, the corresponding channel operates in data and clock
recovery mode. The recovered clock is output on pin RCLKn and re-
timed NRZ data are output on pin RDPn/RDNn in Dual Rail mode or on
RDn in single rail mode. When bit CRSn is set to ‘1’, Dual Rail mode with
data recovery is enabled in the corresponding channel and the clock
recovery is bypassed. In this condition, the analog line signal are
converted to RZ digital bit streams on the RDPn/RDNn pins and inter-
nally connected to an EXOR which is fed to the RCLKn output for
external clock recovery applications.
mode with data recovery. In this case, register e-CRS is ignored.
2.4.3
when the device is configured in Single Rail mode. B8ZS rules for T1
and HDB3 rules for E1 are enabled by setting bit CODE in register GCF
Signals with an attenuation of up to 12 dB (from 2.4 V) can be recov-
The Clock and Data Recovery is accomplished by Digital Phase
The clock recovery and data recovery can be selected on a per
If pin MCLK is pulled high, all the receivers will enter the Dual Rail
Selectable B8ZS/HDB3 and AMI line coding/decoding is provided
CLOCK AND DATA RECOVERY
B8ZS/HDB3/AMI LINE CODE RULE
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
SCLK
SCLK
Interface
Pin SDO
September 22, 2005
Active High
Active High