82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 7

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-1 Pin Description (Continued)
MODE0/CODE
TS1/RD/R/W
IDT82V2044
Pin Description
TS2/SCLK/
CS/JAS
ALE/AS
Name
(Pulled to
VDDIO/2)
Type
I
I
I
I
TQFP144
88
87
86
85
Pin No.
PBGA160
H12
J11
J12
J13
MODE0: Control Mode Select 0
In parallel host mode, the parallel host interface is configured for Motorola compatible hosts when this pin
is low, or for Intel compatible hosts when this pin is high.
CODE: Line Code Rule Select
In hardware control mode, the B8ZS (for T1 mode)/HDB3 (for E1 mode) encoder/decoder is enabled when
this pin is low, and AMI encoder/decoder is enabled when this pin is high. The selections affect all the
channels.
In serial host mode, this pin should be grounded.
CS: Chip Select (Active Low)
In host mode, this pin is asserted low by the host to enable host interface. A high to low transition must
occur on this pin for each read/write operation and the level must not return to high until the operation is
over.
JAS: Jitter Attenuator Select
In hardware control mode, this pin globally determines the Jitter Attenuator position:
TS2: Template Select 2
In hardware control mode, the signal on this pin is the most significant bit for the transmit template select.
Refer to
SCLK: Shift Clock
In serial host mode, the signal on this pin is the shift clock for the serial interface. Data on pin SDO is
clocked out on falling edges of SCLK if pin CLKE is high, or on rising edges of SCLK if pin CLKE is low.
Data on pin SDI is always sampled on rising edges of SCLK.
ALE: Address Latch Enable
In parallel Intel multiplexed host mode, the address on AD[4:0] is sampled into the device on the falling
edges of ALE (signals on AD[7:5] are ignored). In non-multiplexed host mode, ALE should be pulled high.
AS: Address Strobe (Active Low)
In parallel Motorola multiplexed host mode, the address on AD[4:0] is latched into the device on the falling
edges of AS (signals on AD[7:5] are ignored). In non-multiplexed host mode, AS should be pulled high.
TS1: Template Select 1
In hardware control mode, the signal on this pin is the second most significant bit for the transmit template
select. Refer to
RD: Read Strobe (Active Low)
In parallel Intel multiplexed or non-multiplexed host mode, this pin is active low for read operation.
R/W: Read/Write Select
In parallel Motorola multiplexed or non-multiplexed host mode, the pin is active low for write operation and
high for read operation.
VDDIO/2
High
JAS
Low
2.5.1 Waveform Shaper
2.5.1 Waveform Shaper
7
Jitter Attenuator (JA) Configuration
for details.
JA in transmit path
JA in receive path
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
JA not used
for details.
Description
September 22, 2005