82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 44

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-22 TAP Controller State Description (Continued)
IDT82V2044
IEEE STD 1149.1 JTAG Test Access Port
Update-IR
Pause-IR
Exit1-IR
Exit2-IR
State
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-IR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected
by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as
long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-IR state.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-IR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK.
When the new instruction has been latched, it becomes the current instruction. The test data registers selected by the current instruction
retain their previous value.
1
0
Test-logic Reset
Run Test/Idle
0
1
Figure-24 JTAG State Diagram
1
0
Capture-DR
Update-DR
Select-DR
Pause-DR
Exit1-DR
Exit2-DR
Shift-DR
1
44
1
0
1
0
0
1
0
Description
1
1
0
0
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
0
1
Capture-IR
Update-IR
Pause-IR
Select-IR
Exit1-IR
Exit2-IR
Shift-IR
1
1
0
0
0
1
1
0
1
0
1
0
September 22, 2005