82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 18

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-9 Built-in Waveform Template Selection
1.
2.5.2
pin TDNn/BPVIn is used as BPVI input. A low-to-high transition on this
pin inserts a bipolar violation on the next available mark in the transmit
data stream. Sampling occurs on the falling edges of TCLK. But in TAOS
(Transmit All Ones) with Analog Loopback, Remote Loopback and
Inband Loopback, the BPVI is disabled. In TAOS with Digital Loopback,
the BPVI is looped back to the system side, so the data to be transmitted
on TTINGn and TRINGn are all ones with no bipolar violation.
2.6
in receive path or not used. The selection is accomplished by setting pin
JAS in hardware mode or configuring bits JACF[1:0] in register GCF in
host mode which affects all four channels.
needed to be extracted for the internal synchronization, the jitter attenu-
ator is set in the receive path. Another use of the jitter attenuator is to
provide clock smoothing in the transmit path for applications such as
synchronous/asynchronous demultiplexing applications. In these appli-
cations, TCLK will have an instantaneous frequency that is higher than
the nominal T1/E1 data rate and in order to set the average long-term
TCLK frequency within the transmit line rate specifications, periods of
TCLK are suppressed (gapped).
gapped TCLK. In host mode, the FIFO length can be 32 X 2 or 64 X 2
bits by programming bit JADP in GCF. In hardware mode, it is fixed to 64
X 2 bits. The FIFO length determines the maximum permissible gap
width (see
cause FIFO overflow or underflow. The data is 16 or 32 bits’ delay
Maximum cable loss at 772 kHz.
IDT82V2044
Functional Description
When configured in Single Rail Mode 2 with AMI line code enabled,
The jitter attenuator can be selected to work either in transmit path or
For applications which require line synchronization, the line clock
The jitter attenuator integrates a FIFO which can accommodate a
TS2
0
0
0
0
1
1
1
1
BIPOLAR VIOLATION INSERTION
JITTER ATTENUATOR
Table-10 Gap Width
Table-12 External Components Values
1.
For T1 applications, only 5 V VDDT is supported.
TS1
0
0
1
1
0
0
1
1
Component
D1 - D4
TS0
R
Cp
R
0
1
0
1
0
1
0
1
T
R
Limitation). Exceeding these values will
Service
E1
T1
Nihon Inter Electronics - EP05Q03L, 11EQS03L, EC10QS04, EC10QS03L; Motorola - MBR0540T1
9.31 Ω ± 1%
9.5 Ω ± 1%
75 Ω Coax
Clock Rate
2.048 MHz
1.544 MHz
2200 pF
E1
120 Ω Twisted Pair
9.5 Ω ± 1%
15 Ω ± 1%
18
120 Ω/75 Ω Cable
133-266 ft. ABAM
266-399 ft. ABAM
399-533 ft. ABAM
533-655 ft. ABAM
Table-10 Gap Width Limitation
Table-11 Output Jitter Specification
through the jitter attenuator in the corresponding transmit or receive
path. The constant delay feature is crucial for the applications requiring
“hitless” switching.
corner frequency (fc) for both T1 and E1. In hardware mode, the fc is
fixed to 2.5 Hz for T1 or 1.7 Hz for E1. Generally, the lower the fc is, the
higher the attenuation. However, lower fc comes at the expense of
increased acquisition time. Therefore, the optimum fc is to optimize both
the attenuation and the acquisition time. In addition, the longer FIFO
length results in an increased throughput delay and also influences the 3
dB corner frequency. Generally, it’s recommended to use the lower
corner frequency and the shortest FIFO length that can still meet jitter
attenuation requirements.
2.7
TRINGn connections provide a matched interface to the cable.
12
for one transmit/receive channel.
values based on the specific application.
0-133 ft. ABAM
Cable Length
shows the appropriate external components to connect with the cable
The transmit and receive interface RTIPn/RRINGn and TTIPn/
In host mode, bit JABW in GCF determines the jitter attenuator 3 dB
LINE INTERFACE CIRCUITRY
AT&T Pub 62411
Reserved
TR-TSY-000009
GR-253-CODE
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
FIFO Length
64 bit
32 bit
T1
100 Ω Twisted Pair, VDDT = 5.0 V
12.4 Ω ± 1%
9.1 Ω ± 1%
1000 pF
Maximum Cable Loss (dB)
Table-12
T1
(1)
summarizes the component
Max. Gap Width
ETSI CTR 12/13
0.6
1.2
1.8
2.4
3.0
September 22, 2005
-
-
ITU-T G.736
ITU-T G.742
ITU-T G.783
56 UI
28 UI
E1
(1)
Figure-