LAN91C111-NU Standard Microsystems (SMSC), LAN91C111-NU Datasheet - Page 34

• Manufacturer Part Number: LAN91C111-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN91C111-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Revision 1.91 (06-01-09)
TP Squelch - 100 Mbps
The squelch block determines if the TP input contains valid data. The 100 Mbps TP squelch is one
of the criteria used to determine link integrity. The squelch comparators compare the TP inputs against
fixed positive and negative thresholds, called squelch levels. The output from the squelch comparator
goes to a digital squelch circuit which determines if the receive input data on that channel is valid. If
the data is invalid, the receiver is in the squelched state. If the input voltage exceeds the squelch
levels at least 4 times with alternating polarity within a 10 μS interval, the data is considered to be
valid by the squelch circuit and the receiver now enters into the unsquelch state. In the unsquelch
state, the receive threshold level is reduced by approximately 30% for noise immunity reasons and is
called the unsquelch level. When the receiver is in the unsquelch state, then the input signal is
deemed to be valid. The device stays in the unsquelch state until loss of data is detected. Loss of
data is detected if no alternating polarity unsquelch transitions are detected during any 10 μS interval.
When the loss of data is detected, the receive squelch is turned on again.
TP Squelch, 10 Mbps
The TP squelch algorithm for 10 Mbps mode is identical to the 100 Mbps mode except, (1) the 10
Mbps TP squelch algorithm is not used for link integrity but to sense the beginning of a packet, (2) the
receiver goes into the unsquelch state if the input voltage exceeds the squelch levels for three bit times
with alternating polarity within a 50-250 nS interval, (3) the receiver goes into the squelch state when
idle is detected, (4) unsquelch detection has no affect on link integrity, link pulses are used for that in
10 Mbps mode, (5) start of packet is determined when the receiver goes into the unsquelch state an
a CRS100 is asserted, and (6) the receiver meets the squelch requirements defined in IEEE 802.3
Clause 14.
0
Figure 7.5 TP Input Voltage Template -10MBPS
585 mV sin (2
0
PW/4
585 mV sin (
Slope 0.5 V/ ns
Slope 0.5 V/ ns
585 mV sin [2
a. Short Bit
b. Long Bit
*
DATASHEET
t/PW)
34
*
t/PW)
(t - PW/2)/PW]
3PW/4
P W
10/100 Non-PCI Ethernet Single Chip MAC + PHY
3.1V
585mV
PW
585mV
3.1V
SMSC LAN91C111 REV C
Datasheet