AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet
AM79C976KI
Specifications of AM79C976KI
Related parts for AM79C976KI
AM79C976KI Summary of contents
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PRELIMINARY Am79C976 PCnet-PRO™ 10/100 Mbps PCI Ethernet Controller DISTINCTIVE CHARACTERISTICS I Integrated Fast Ethernet controller for the Peripheral Component Interconnect (PCI) bus — 32-bit glueless PCI host interface — Supports PCI clock frequency from MHz independent of ...
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I Dual-speed CSMA/CD (10 Mbps and 100 Mbps) Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 and Blue Book Ethernet standards I Programmable internal/external loopback capabilities I Supports patented External Address Detection Interface (EADI) with receive frame tagging support for ...
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GENERAL DESCRIPTION The Am79C976 controller is a highly-integrated 32-bit full-duplex, 10/100-Megabit per second (Mbps) Ether- net controller solution, designed to address high- performance system application requirements flexible bus mastering device that can be used in any application, ...
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BLOCK DIAGRAM CLK RST AD[31:0] C/BE[3:0] PAR FRAME TRDY IRDY STOP IDSEL DEVSEL PCI Bus REQ Interface GNT Unit PERR SERR INTA EECS 93CXX EESK EEPROM EEDI Interface EEDO TCK JTAG TMS Port TDI Control TDO ...
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TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Re-Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Enabling Traffic Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PCI Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LED3 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CSR50-57: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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BCR42: PCI DATA Register Five (DATA5) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 BCR43: ...
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APPENDIX B: MII MANAGEMENT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIST OF FIGURES Figure 1: Slave Configuration Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 49: CLK Waveform for 5 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 ...
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LIST OF TABLES Table 1: System Clock Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 49: CTRL3: Control3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 98: R/TLEN Decoding (SSIZE32 = 228 Table ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79C976 K C/D/I Valid Combinations Am79C976 KC/W KD/W KI ...
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CONNECTION DIAGRAM (PQR208) AD30 1 AD29 2 VDD 3 AD28 4 AD27 5 AD26 6 VSSB 7 AD25 8 AD24 9 C/BE3 10 VDD 11 IDSEL 12 AD23 13 AD22 14 15 VSSB 16 AD21 VSS 17 AD20 18 AD19 ...
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PIN DESIGNATIONS (PQR208) Listed By Pin Number Pin No. Pin Name Pin No. 1 AD30 53 2 AD29 54 3 VDD 55 4 AD28 56 5 AD27 57 6 AD26 58 7 VSSB 59 8 AD25 60 9 AD24 61 ...
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Pin No. Pin Name Pin No. 35 SERR 87 36 PAR 88 37 VDD 89 38 C/BE1 90 39 AD15 91 40 AD14 92 41 VSSB 93 42 AD13 94 43 AD12 95 44 AD11 96 45 VDD 97 46 ...
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PIN DESIGNATIONS Listed By Group Pin Name Pin Function Clock Interface XTAL1 Crystal XTAL2 Crystal XCLK External Clock CLKSEL0 Clock Select CLKSEL1 Clock Select CLKSEL2 Clock Select TEST Test Select PCI Bus Interface AD[31:0] Address/Data Bus C/BE[3:0] Bus Command/Byte Enable ...
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Pin Name Pin Function EECS Serial EEPROM Chip Select EEDI Serial EEPROM Data In EEDO Serial EEPROM Data Out EESK Serial EEPROM Clock External Memory Interface ERCLK External Memory Clock ERA[19:0]/FLA[19:0] External Memory Address[19:0] External Memory Data [31:0]/Flash ERD[31:0] / ...
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Pin Name Pin Function VAUX_SENSE Vaux Sense IEEE 1149.1 Test Access Port Interface (JTAG) TCK Test Clock TDI Test Data In TDO Test Data Out TMS Test Mode Select Power Supplies VDD Digital and I/O Buffer Power VSS Digital Ground ...
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PIN DESCRIPTIONS PCI Interface AD[31:0] Address and Data Address and data are multiplexed on the same bus in- terface pins. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During the subsequent clocks, AD[31:0] contain ...
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By default INTA is an open-drain output. For applica- tions that need an active-high edge-sensitive interrupt signal, the INTA pin can be configured for this mode by setting INTLEVEL (CMD3, bit 13 or BCR2, bit IRDY Initiator ...
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PME Power Management Event Output, Open Drain PME is an output that can be used to indicate that a power management event (a Magic Packet, an OnNow pattern match change in link state) has been de- tected. The ...
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Change Detect mode and a Link Change has been de- tected. This pin can drive the external system management logic that causes the CPU to get out of a low power mode of operation. This pin is implemented for designs ...
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If the CLKSEL0 and CLKSEL1 pins are not both held low, a 20-, 25-, or clock source must be con -MHz / 3 nected to the XCLK pin, and the XTAL1 and XTAL2 pins should be connected to ...
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All FLA[23:20] pin outputs are forced to a constant level to conserve power while no access on the External Memory Bus is being performed. Note: The FLA[23:20] pins are multiplexed with the ERD[11:8] pins. ERD[31:0]/FLD[7:0] External Memory Data [31:0] The ...
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CRS Carrier Sense CRS is an input that indicates that a non-idle medium, due either to transmit or receive activity, has been de- tected. RX_CLK Receive Clock RX_CLK is a clock input that provides the timing refer- ence for the ...
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Data on the RXD[3:0] will be the start of the destination address field. SFBD will subsequently toggle every nib- ble time (1.25 MHz frequency when operating at 10 Mbps and 12.5 MHz frequency when operating at 100 Mbps), indicating the ...
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BASIC FUNCTIONS System Bus Interface The Am79C976 controller is designed to operate as a bus master during normal operations. Some slave I/O accesses to the Am79C976 controller are required in normal operations as well. Initialization of the Am79C976 controller is ...
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DETAILED FUNCTIONS Slave Bus Interface Unit The slave bus interface unit (BIU) controls all accesses to the PCI configuration space, the Control and Status Registers (CSR), the Bus Configuration Registers (BCR), the Address PROM (APROM) locations, and the Expansion ROM. ...
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DEVSEL is asserted two clock cycles after the host has asserted FRAME. See Figure 1 and Figure 2. CLK FRAME ADDR AD C/BE 1010 BE PAR PAR IRDY TRDY DEVSEL STOP ...
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CLK 1 2 FRAME AD ADDR C/BE 0010 PAR IRDY TRDY DEVSEL STOP Figure 3. Slave Read Using I/O Command PAR Am79C976 ...
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CLK 1 2 FRAME ADDR AD 0111 C/BE PAR PAR IRDY TRDY DEVSEL STOP Figure 4. Slave Write Using Memory Command 9/14/ DATA BE ...
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Expansion ROM Transfers The Am79C976 device includes an interface to an op- tional expansion ROM. The amount of PCI address space claimed by this ROM is determined by the con- tents of the ROM Configuration Register, ROM_CFG, which should normally ...
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CLK FRAME ADDR DATA AD CMD BE C/BE PAR PAR IRDY TRDY DEVSEL STOP Figure 5. Disconnect Of Slave Cycle When Busy Disconnect Of Burst Transfer The Am79C976 controller does not support burst ac- cess to the ...
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CLK FRAME AD 1st DATA DATA C/BE BE PAR PAR IRDY TRDY DEVSEL STOP Figure 7. Disconnect Of Slave Burst Transfer - Host Inserts Wait States Parity Error Response When the Am79C976 controller is not the ...
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CLK 1 FRAME AD C/BE PAR PERR IRDY TRDY DEVSEL Figure 9. Slave Cycle Data Parity Error Response Master Bus Interface Unit The master Bus Interface Unit (BIU) controls the acqui- sition of the PCI bus and all accesses to ...
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C[3:0] Command 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual ...
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CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled The FIFO thresholds should be greater than or equal to the cache line size to maximize the use of the MRL and MRM commands. If the ...
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CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled ADDR DATA 1110 0000 PAR PAR Figure 12. ...
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CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Basic Burst Write Transfer The Am79C976 controller supports burst mode for all bus master write operations. To allow burst transfers in descriptor write operations, the Am79C976 ...
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The following three data phases take one clock cycle each, which is deter- mined by the timing of TRDY. DMA Burst Alignment The BIU ...
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CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL STOP REQ GNT DEVSEL is sampled Figure 15. Disconnect With Data Transfer Disconnect Without Data Transfer Figure 16 shows a target disconnect sequence during which no data is transferred. STOP is ...
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CLK 1 2 FRAME AD C/BE PAR IRDY TRDY DEVSEL STOP REQ GNT DEVSEL is sampled Figure 16. Disconnect Without Data Transfer Target Abort Figure 17 shows a target abort sequence. The target asserts DEVSEL for one clock. It then ...
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FRAME C/BE IRDY TRDY DEVSEL STOP RTABORT (PCI Status register, bit 12) will be set to indicate that the Am79C976 controller has received a target abort. In addition, SINT (CSR5, bit 11) will be set to 1. When SINT is ...
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CLK FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT Figure 18. Preemption During Non-Burst Transaction If the controller is executing a Memory Write and Inval- idate instruction when preemption occurs, the control- ler will finish writing the current cache ...
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CLK FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT Figure 19. Preemption During Burst Transaction 9/14/ ADDR DATA DATA DATA DATA 0111 ...
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CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Parity Error Response During every data phase of a DMA read operation, when the target indicates that the data is valid by as- serting TRDY, the ...
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CLK 1 FRAME AD C/BE PAR PERR IRDY TRDY DEVSEL Figure 21. Master Cycle Data Parity Error Response Whenever the Am79C976 controller is the current bus master and a data parity error occurs, SINT (CSR5, bit 11) will be set ...
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CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 22. Descriptor Ring Read In Non-Burst Mode When SWSTYLE is set the descriptor en- tries are ordered to allow burst ...
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CLK FRAME AD MD1 DATA C/BE 0110 0000 PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 23. Descriptor Ring Read In Burst Mode Table 4 shows the descriptor read sequence. During descriptor write ...
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Table 5. Descriptor Write Sequence SWSTYLE BCR20[7: AD Bus Sequence AD Bus Sequence 0] for Rx Descriptor for Tx Descriptor Address = XXXX Address = XXXX XX04h XX04h Data Data 0 Idle Idle Address = XXXX Address = XXXX XX00h ...
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CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 24. Descriptor Ring Write In Non-Burst Mode 9/14/ ...
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CLK FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT Figure 25. Descriptor Ring Write In Burst Mode FIFO DMA Transfers Am79C976 logic will determine when a FIFO DMA transfer is required. This transfer mode will be used for transfers ...
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CLK FRAME AD ADD DATA 0111 0001 C/BE PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 26. FIFO Burst Write At Start Of Unaligned Buffer 9/14/ ...
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Am79C976 9/14/00 ...
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CLK FRAME AD ADD DATA 0111 C/BE PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 27. FIFO Burst Write At End Of Unaligned Buffer Note that the Am79C976 controller will always perform a ...
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Re-Initialization Earlier members of the PCnet family of controllers had to be re-initialized if the transmitter and/or the receiver were not turned on during the original initialization, and it was subsequently required to activate them ei- ther section ...
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CSR5/CSR7 method with the CMD0 method. For compatibility with other PCnet family devices, after the SPND bit in CSR5 is set, it will read back a one only after the suspend operation is complete, that is, ...
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I The length of the message buffer I Status information indicating the condition of the buffer To permit the queuing and de-queuing of message buffers, ownership of each buffer is allocated to either the Am79C976 controller or the host. The ...
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Note that in this mode the value of CSR2, bits 15-8, is used as the upper 8-bits for all memory addresses dur- ing bus master transfers. . CSR2 IADR[31:16] IADR[15:0] Initialization Block TLEN RLEN TLE RES RLE RES PADR[31:0] PADR[47:32] ...
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Receive descriptor polling will continue even if transmit polling is disabled by setting TXDPOLL least two receive descriptors are owned by the Am79C976 con- troller there will be no descriptor polling if there is no network activity. The ...
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By default, whenever the DMA controller finishes copy- ing a transmit frame from system memory, it sets the TINT bit of CSR0 to indicate that the buffers are no longer needed. This causes an interrupt signal if the IENA bit ...
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This behavior allows the host software to pre-assign buffer space in such a manner that the header portion of a receive ...
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In that case, the SFD will be the first two nibbles received. Once the SFD is detected, all subsequent nibbles are treated as part of the frame. The MAC en- gine will inspect the length field to ensure minimum ...
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Part1 (IFS1) time of 60 bit times and an Inter- FrameSpacingPart 2 time of 36 bit times. The Am79C976 controller will perform the two-part de- ferral algorithm as specified in Clause 4.2.8 of IEEE Std 802.3 (Process Deference). The Inter ...
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However, if the RTRY_LCOL bit is cleared retry attempt will be scheduled on detection of a late collision. In this case, the transmit message will be flushed ...
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The transmit frame will be padded by bytes with the value of 00H. The default value of APAD_XMT is 0 after H_RESET, which will disable au- tomatic pad generation. If automatic pad generation is disabled, the software ...
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FIFO underflow error occurs. Instead, it will wait until the entire frame has been copied into the transmit FIFO, and then it will restart the transmission process. Loss of Carrier The XmtLossCarrier counter is incremented if transmit is attempted ...
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DRCVBC (CSR15, bit 14) is set. DRCVBC overrides a logical address match. If DRCVBC is set to 1, broadcast frames are not ac- cepted even if the Logical Address Filter is pro- grammed in such a ...
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Bits Bits Preamble SFD Destination 1010....1010 10101011 Address Start of Frame at Time = 0 Increasing Time Figure 31. IEEE 802.3 Frame and Length Field Transmission Order Since any valid Ethernet Type field value will always be greater ...
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PCI memory space and can not be accessed indirectly through the RAP and RDP registers. To simplify the use of software debuggers, the counter logic is designed so that the statistics counters can be accessed one, two, or ...
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Offset (hex) Receive Counter Name 10 RcvUndersizePkts 14 RcvOversizePkts 18 RcvFragments 1C RcvJabbers 20 RcvUnicastPkts 24 RcvAlignmentErrors 28 RcvFCSErrors 2C RcvGoodOctets 30 RcvMACCtrl 34 RcvFlowCtrl 40 RcvPkts64Octets 44 RcvPkts65to127Octets 9/14/ ...
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Offset (hex) Receive Counter Name 48 RcvPkts128to255Octets 4C RcvPkts256to511Octets 50 RcvPkts512to1023Octets 54 RcvPkts1024to1518Octets 58 RcvUnsupportedOpcodes 5C RcvSymbolErrors Transmit Statistics Counters Table 8 describes the statistics counters associated with the transmitter and lists the MIB objects that these counters support. In ...
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Offset (hex) Transmit Counter Name RMON etherStatsPkts RMON etherHistoryPkts 68 XmtPackets RMON hostOutPkts RMON hostTimeOutPkts BRIDGE-MIB dot1dTpPortOutFrames RMON etherStatsBroadcastPkts RMON etherHistoryBroadcastPkts 6C XmtBroadCastPkts RMON hostOutBroadcastPkts RMON hostTimeOutBroadcastPkts EXT-MIB-II ifOutBroadcastPkts RMON etherStatsMulticastPkts RMON etherHistoryMulticastPkts 70 XmtMultiCastPkts RMON hostOutMulticastPkts RMON hostTimeOutMulticastPkts EXT-MIB-II ...
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Offset (hex) Transmit Counter Name 98 XmtBackPressure 9C XmtFlowCtrl PAUSEMACCtrlFramesTransmitted A0 XmtPkts64Octets RMON etherStatsPkts64Octets A4 XmtPkts65to127Octets RMON etherStatsPkts65to127Octets A8 XmtPkts128to255Octets RMON etherStatsPkts128to255Octets AC XmtPkts256to511Octets RMON etherStatsPkts256to511Octets B0 XmtPkts512to1023Octets RMON etherStatsPkts512to1023Octets B4 XmtPkts1024to1518Octets RMON etherStatsPkts1024to1518Octets B8 XmtOversizePkts VLAN Support Virtual Bridged ...
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OCTETS 1 OCTET DESTINATION ADDRESS 6 OCTETS SOURCE ADDRESS 6 OCTETS LENGTH/TYPE = 8100h 2 OCTETS TAG CONTROL INFORMATION 2 OCTETS MAC CLIENT LENGTH/TYPE 2 OCTETS 42-1500 OCTETS MAC CLIENT DATA FRAME CHECK SEQUENCE 4 OCTETS The Am79C976 device ...
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Table 9. VLAN Tag Control Command TCC (TMD2[17:16]) Action 00 Transmit data in buffer unaltered 01 Delete Tag Header Insert Tag Header containing TCI 10 field from descriptor. Replace TCI field from buffer with TCI 11 data from descriptor. Table ...
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Transmission is not deferred while receive is active. — The IPG counter which governs transmit deferral during the IPG between back-to-back transmits is started when transmit activity for the first packet ends, instead of when transmit and car- rier ...
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The receive process starts when RX_DV is asserted. RX_DV must remain asserted until the end of the re- ceive frame. If the external PHY device detects errors in the currently received frame, it asserts the RX_ER signal. RX_ER can be ...
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Frame is a preamble of 32 ones that guaran- tees that all of the external PHYs are synchronized on the same interface. (See Figure 34.) Loss of synchro- nization is possible due to the hot-plugging capability of OP Preamble ...
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PHY Access Register can be read at any time, and the PHY_CMD_DONE bit in that register indicates whether or not PHY_DATA field contains valid data. To generate a non-blocking read from a PHY register the ...
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Auto-Poll Data Register without caus- ing an interrupt. When the contents of one of the selected PHY regis- ters changes, the corresponding Auto-Poll Data Regis- ter is updated so that another interrupt will occur when the data changes ...
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Auto-Negotiation goes further by providing a message- based communication scheme called, Next Pages, be- fore connecting to the Link Partner. The Network Port Manager does not support this feature. However, the host CPU can disable the Network Port Manager and ...
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Management Interface connection, in which case the Port Manager is not able to start the auto-negotiation process or set up the MAC-based on auto-negotiation results. This may happen if the Am79C976 controller is connected to a multi-PHY device that has ...
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I Negotiate Pause Ability (NPA) bit I Force Pause Ability (FPA) bit. The duplex mode affects the type of traffic regulation that is used. In full-duplex mode the FC pin and the FCPEN, FCCMD, and FIXP bits control the transmis- ...
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The effects of the FCCMD bit are summarized in Table 14. Table 14. FCCMD Bit Functions FCCMD Duplex Transition FIXP Mode Half Enable back pressure Half Disable back pressure Send pause frame ...
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External Address Detection Interface The EADI is provided to allow external address filtering and to provide a Receive Frame Tag word for propri- etary routing information. This feature is typically uti- lized by terminal servers, switches and/or router products. The ...
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If SWSTYLE = tag bits are shifted in the order B14, B13, ... , B0. Because of the order in which frame tag bits are shifted in, if the tag is shorter than 15 bits, the tag ...
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The higher 4 bits of address for the Flash memory are shared with bits [11:8] of the SSRAM data bus (ERD[11:8]). The lower 8 bits of the external memory data bus ERD[7:0] are used by both the SSRAM and the ...
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The timing diagram in Figure 37 assumes the default programming of ROMTMG (1001b = 9 CLK). After reading the first byte, the Am79C976 controller reads in three more bytes by incrementing the lower portion of the ROM address. The PCI ...
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The Am79C976 controller aliases all accesses to the Expansion ROM of the command types Memory Read Multiple and Memory Read Line to the basic Memory Read command. Since setting MEMEN also enables memory mapped access to the I/O resources, attention ...
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ROMCLK ERA[19:0] ERD[7:0] FLCS FLOE FLWE SRAM Configuration The Am79C976 controller uses external SSRAM for re- ceive and transmit FIFOs. The size of the SSRAM can Mbytes, organized bits. The size of ...
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CPU requests an EEPROM read operation. Note that if the EEPROM is not included in the system, the MAC address (and Magic Packet information, if needed) must be initialized by ...
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Entry for 1 register Byte 127 Bit: Word 0 Word 1 Note: All registers are restored to their default values, not just those registers that were altered by the EE- PROM read operation. If the Am79C976 device detects a correct ...
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The automatic read operation takes about 180 µs for each 16-bit register that is initialized plus 180 µs for the CRC code word. EEPROM Auto-Detection When the address field ...
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LED register asynchronously sets all three bits of its shift register when the output becomes asserted. The inverted output of each shift register is used to control an LED pin. Thus, the pulse stretcher provides 2 to ...
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I PCI Bus Power Management Interface Specifica- tion (OnNow) wake-up I RWU (hardware controlled) wake-up All three wake-up events and both control mechanisms support wake-up from any power state including D3 Magic Packet MPPEN_EE MPPEN_SW PG MPEN_EE MPEN_SW Link Change ...
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The type of wake-up is configured by software using the bits LCMODE_SW, PMAT_MODE, MPEN_SW and MPPEN_SW in the CMD7 register. These bits are only reset by the power-on reset (POR) and are not loaded from the EEPROM so that they ...
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Am79C976 controller will not start where it left off. If Magic Packet mode is disabled by the assertion of PG, then in order to immediately re-enable Magic Packet mode, ...
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BCR BCR Bit Number PMAT1 PMR_B4 Pattern Match RAM Address pointer 1 P7 pointer 2 Data Byte 3 2+n Data Byte 4n+3 Date Byte 4n+2 J Data Byte 3 ...
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Table 17. IEEE 1149.1 Supported Instruction Summary Instruc- Instruction tion Name Code Description External EXTEST 0000 Test ID Code IDCODE 0001 Inspection Sample SAMPLE 0010 Boundary TRIBYP 0011 Force Float Control SETBYP 0100 Boundary To 1/0 Bypass BYPASS 1111 Scan ...
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S_RESET S_RESET is provided for compatibility with previous PCnet family devices. S_RESET occurs when the host CPU reads the Reset register, which is located at offset 14h if the device is operating in Word I/O mode or at off- set ...
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Software Access PCI Configuration Registers The Am79C976 controller implements the 256-byte configuration space as defined by the PCI specification revision 2.1. The 64-byte header includes all registers required to identify the Am79C976 controller and its function. Additionally, the optional PCI ...
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The MEMEN bit in the PCI Command register must also be set to enable the mode. Both base address registers can be active at the same time. The Am79C976 controller requires that the memory space ...
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Word I/O Mode After H_RESET, the Am79C976 controller is pro- grammed to operate in Word I/O mode. DWIO (BCR18, bit 7) will be cleared to 0. Table 22 shows how the 32 bytes of address space are used in Word ...
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Table 23. Legal I/O Accesses in Word I/O Mode (DWIO = 0) AD[4:0] BE[3:0] Type 0XX00 1110 RD 0XX01 1101 RD 0XX10 1011 RD 0XX11 0111 RD 0XX00 1100 RD 0XX10 0011 RD 10000 1100 RD 10010 0011 RD 10100 ...
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Table 25. Legal I/O Accesses in Double Word I/O Mode (DWIO =1) 10100 0000 RD DWord read of RAP DWord read of Reset 11000 0000 RD Register 112 Am79C976 ...
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USER ACCESSIBLE REGISTERS The Am79C976 controller has four types of user regis- ters: the PCI configuration registers, the memory- mapped registers, the Control and Status registers (CSRs), and the Bus Control registers (BCRs). The CSRs and BCRs are included for ...
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The PCI Command register is read and written by the host. Bit Name Description 15-10 RES Reserved locations. Read as ze- ros; write operations have no ef- fect. 9 FBTBEN Fast Back-to-Back Enable. When this bit is set to 1, ...
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MEMEN. The Am79C976 controller will only respond to ac- cesses to the Expansion ROM when both ROMEN (PCI Expan- sion ROM Base Address register, bit 0) and MEMEN are set to 1. Since MEMEN also enables the memory mapped ...
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Writing a 0 has no effect. RTABORT is cleared by H_RESET and is not affected by S_RESET or by set- ting the STOP bit. 11 STABORT Send Target Abort. Read as ze- ro; write operations ...
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PCI Cache Line Size Register Offset 0Ch This register indicates the system cache line size in units of 32-bit double words. This quantity is used to determine when to use the advanced PCI bus com- mands (MWI, MRL, and MRM). ...
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When the host writes a value of FFFF FFFFh to the I/O Base Address register, it will read back a value bits 4-2. That indicates an space requirement of 32 bytes. 1 RES Reserved location. ...
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alias of BCR23, bits 15- programmable through the EEPROM. The PCI Subsystem Vendor ID register is read only. PCI Subsystem ID Register Offset 2Eh The PCI Subsystem ID register is a 16-bit register that together ...
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Bit Name Description 31-24 ROMBASE Expansion ROM base address most significant 8 bits. These bits are written by the host to specify the location of the Expansion ROM in PCI memory space. ROMBASE must be written with a valid address ...
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EEPROM recommended that the shadow register be pro- grammed to a value of 18h, which corresponds to 6 µs. The host should use the value in this register to deter- ...
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PME_CLK PME Clock. When this bit indicates that the function relies on the presence of the PCI clock for PME operation. When this bit indicates that no PCI clock is required ...
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Power State. This 2-bit field is used both to determine the cur- rent power state of a function and to set the function into a new power state. The definition of the field values is as follows: 00b - D0 ...
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Memory-Mapped Registers The Memory-Mapped Registers give the host CPU ac- cess to all programmable features of the Am79C976 device. These registers are mapped directly into PCI memory space so that any programmable feature can be accessed with a single PCI ...
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Table 27. AP_VALUE1: Auto-Poll Value1 Register Bit Name Description This register contains the results of AP_VALUE the automatic polling of the user- 15-0 1 selectable external PHY register, AP_REG1. AP_VALUE2: Auto-Poll Value2 Register Offset 0ACh The contents of this register ...
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Bit Name 15 AP_REG0_EN Enable Bit for Autopoll Register 0. This bit is read-only and always has the value 1. 14-13 RES Reserved locations. Written as zeros and read as undefined AP_REG0_ 12-8 AP_REG0 Address. This field is read-only and ...
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AUTOPOLL2: Auto-Poll2 Register Offset 08Ch This register controls the automatic polling of a user- selectable external PHY register, AP_REG2. Table 34. AUTOPOLL2: Auto-Poll2 Register Bit Name Enable Bit for Autopoll Register 2. When this bit and the Auto-Poll External PHY ...
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AUTOPOLL3: Auto-Poll3 Register Offset 08Eh This register controls the automatic polling of a user- selectable external PHY register, AP_REG3. Table 35. AUTOPOLL3: Bit Name Enable Bit for Autopoll Register 3. When this bit and the Auto-Poll External PHY bit (APEP) ...
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AUTOPOLL4: Auto-Poll4 Register Offset 090h This register controls the automatic polling of a user- selectable external PHY register, AP_REG4. Table 36. AUTOPOLL4: Auto-Poll4 Register Bit Name Enable Bit for Autopoll Register 4. When this bit and the Auto-Poll External PHY ...
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AUTOPOLL5: Auto-Poll5 Register Offset 092h This register controls the automatic polling of a user- selectable external PHY register, AP_REG5. Table 37. Bit Name Enable Bit for Autopoll Register 5. When this bit and the Auto-Poll External PHY bit (APEP) in ...
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BADX: Transmit Ring Base Address Register Offset 100h This 64-bit register allows the Transmit Descriptor Ring to be located anywhere in a 64-bit address space. For systems with a 32-bit or smaller address space only necessary to program ...
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CMD0: Command0 Offset 048h Bit Name 31-16 RES Reserved locations. Written as zeros and read as undefined. Value bit for byte 1. The value of this bit is written to any bits in the CMD0 register that correspond 15 VAL1 ...
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Bit Name Receive Suspend. Setting this bit causes the receiver to suspend its activities without stopping in the middle of a frame reception. After the receiver suspends its activities, the DMA controller continues copying data from the Receive FIFO into ...
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Bit Name LED Program Enable. When LEDPE is set to 1, programming of the LED functions through BCR4, BCR5, BCR6, and BCR7 is enabled. When LEDPE is cleared to 0, programming of LED functions through these registers is disabled. Writes ...
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Bit Name Value bit for byte 1. The value of this bit is written to any bits in the CMD2 register that correspond 15 VAL1 to bits in the CMD2[14:8] bit map field that are set RES ...
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Bit Name Internal Loopback. When this bit is set, the transmitter is internally connected to the receiver so that the TXD[3:0] outputs are connected internally to the RXD[3:0] inputs, the TX_EN output is connected to the RX_DV input, and RX_CLK ...
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CMD3: Command3 Offset 054h Bit Name Value bit for byte 3. The value of this bit is written to any bits in the CMD3 register that correspond 31 VAL3 to bits in the CMD3[30:24] bit map field that are set ...
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Bit Name Admit Only VLAN Frames. When this bit is set to 1, only frames with a VLAN Tag Header 19 VLONLY containing a non-zero VLAN ID field will be received. All other frames will be rejected. Retransmit on Retry ...
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Bit Name Receive Frame Tag Enable. When this bit is set, frame tag data that is shifted in through the 10 RXFRTGEN External Address Detection Interface (EADI) while a frame is being received will be copied to the receive descriptor. ...
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CMD7: Command7 Offset 064h CMD7 is a command-style register. All bits in this reg- ister are cleared to 0 when power is first applied to the device (power-on reset). The contents of this register Bit Name 31-8 RES Reserved locations. ...
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CTRL0: Control0 Register Offset 068h This register contains several miscellaneous control bits. Each byte of this register controls a single func- tion not necessary read-modify-write oper- ation to change a function’s settings if only a ...
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Bit Name Expansion ROM Timing. The value of ROMTMG is used to tune the timing for all accesses to the external Flash/EPROM. ROMTMG defines the amount of time that a valid address is driven on the ERA[19:0] pins. The register ...
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Bit Name Transmit Start Point. XMTSP controls the point at which preamble transmission attempts to commence in relation to the number of bytes written to the MAC Transmit FIFO for the current transmit frame. When the entire frame is in ...
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Bit Name 7-2 RES Reserved locations. Written as zeros and read as undefined. Receive FIFO Watermark. RCVFW controls the point at which receive DMA is requested in relation to the number of received bytes in the Receive FIFO. RCVFW specifies ...
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CTRL2: Control2 Register Offset 070h This register contains several miscellaneous control bits. Each byte of this register controls a single func- tion not necessary read-modify-write oper- ation to change a function’s settings if only a ...
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Bit Name External PHY Speed. When set, this bit will force the external PHY into 100 Mbps mode when Auto- Negotiation is not enabled. 3 XPHYSP XPHYSP is only valid when the internal Network Port Manager is scanning for a ...
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SWSTYLE Style [7:0] Name LANCE/ 00h PCnet-ISA controller 01h RES 02h PCnet-PCI controller PCnet-PCI 03h controller 04h VLAN 05h 64-bit address All Other Reserved DATAMBIST: Memory Built-in Self-Test Access Register Offset 1A0h This register is used to control and indirectly ...
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Bit Name MBIST Test Failure Indicator. This bit is set when a memory test error is detected reset when DM_START is set not cleared when DM_RESUME is set DM_TEST_FAIL This bit ...
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Reerved Register Offset 0C0h Bit Name 31-21 RES Reserved. Written as 0, read as undefined. 20-16 RES Reserved. Written as 0, read as undefined. 15-11 RES Reserved. Written as 0, read as undefined. 10-0 RES Reserved. Written as 0, read ...
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EEPROM_ACC: EEPROM Access Register Offset 17Ch Table 53. EEPROM_ACC: EEPROM Access Register Bit Name EEPROM Valid status bit. PVALID is read only; write operations have no effect. A value this bit indicates that a PREAD operation has ...
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Bit Name EEPROM Port Enable. When this bit is set causes the values of ECS, ESK, and EDI to be driven onto the EECS, EESK, and EEDI pins, respectively. If EEN = 0 and no EEPROM ...
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FLASH_ADDR: Flash Address Register Offset 198h Table 55. FLASH_ADDR: Flash Address Register Bit Name Lower Address Auto Increment. When the LAAINC bit is set to 1, the low-order 16-bit portion of the Flash Address Register will automatically increment by one ...
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FLOW: Flow Control Register Offset 0C8h Bit Name 31-24 RES Reserved locations. Written as zeros and read as undefined. Value bit for byte 2. The value of this bit is written to any bits in the FLOW register that correspond ...
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Bit Name 16 FCCMD Flow Control Command. In full-duplex mode this bit allows the host CPU to cause a Pause Frame to be sent by issuing a single command. In half-duplex mode, setting this bit puts the device into back-pressure ...
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INT0: Interrupt0 Offset 038h INT0 identifies the source or sources of an interrupt. With the exception of INTR, all bits in this register are “write 1 to clear” so that the CPU can clear the interrupt condition by reading the ...
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Bit Name MII Management Read Error Interrupt. The MII Read Error interrupt is set by the Am79C976 controller to indicate that the currently read register from the external PHY is invalid. The contents of the PHY Access Register are incorrect ...
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INTEN0: Interrupt0 Enable Offset 040h This register allows the software to specify which types of interrupt events will cause the INTR bit in the Interrupt0 register to be set, which in turn will cause INTA pin to be asserted if ...
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Bit Name Magic Packet Interrupt Enable. When this bit is set, the INTR bit will be set when the MPINT bit in INT0 is set. 13 MPINTEN This bit is an alias of CSR5, bit 3. System Interrupt Enable. When ...
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IPG: Inter-Packet Gap Register Offset 18Dh Bit Name Inter Packet Gap. This value indicates the minimum number of network bit times after the end of a frame that the transmitter will wait before it starts transmitting another frame. In half-duplex ...
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LED0 Control Register Offset 0E0h This register controls the function(s) that the LED0 pin displays. Multiple functions can be simultaneously en- abled on this LED pin. The LED display will indicate the logical OR of the enabled functions. This register ...
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Bit Name Receive Match Status Enable. When this bit is set, a value passed to the LEDOUT bit in this register when there is receive activity on the network that has passed the address match function for ...
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MAX_LAT_A: PCI Maximum Latency Alias Register Offset 1B1h This register is a writable alias of the Maximum Latency field at offset 3Fh in PCI configuration space, which is read only. The purpose of this register is to allow the Table ...
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Bit Name MAC Physical Address, PADR[47:0]. This register contains 48-bit, globally unique station address assigned to this device. If the least significant bit of the first byte of a received frame is 0, the destination address of the frame is ...
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This register is an alias of BCR38. The contents of this register are cleared to 0 when the RST pin is asserted, before the serial EEPROM is read, and after a serial EEPROM read error. PCIDATA2: PCI DATA Register Two ...
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PHY Access Register Offset 0D0h This register gives the host CPU indirect access to the MII Management Bus (MDC/MDIO). Through this reg- ister the host CPU can read or write any external PHY Table 69. Bit Name PHY Command Complete. ...
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PMAT0: OnNow Pattern Register 0 Offset 190h This register is used to control and indirectly access the Pattern Match RAM (PMR). When the PMAT_MODE bit (CMD7, bit3 Pattern Match logic is enabled. No bus accesses into PMR are ...
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PMC_A: PCI Power Management Capabilities Alias Register Offset 1B8h This register is an alias of the PMC register located at offset 42h of the PCI Configuration Space. Since the PMC register is read only, this register provides a means of ...
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ROM_CFG: ROM Base Address Configuration Register Offset 18Eh This register, which should normally be loaded from the serial EEPROM, determines which bits in the Expan- sion ROM Base Address Register (ROMBASE) in PCI Configuration Space can be altered by PCI ...
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SRAM Boundary Register Offset 17Ah Bit Name SRAM Boundary. Specifies the size of the transmit buffer portion of the SRAM in units of 512-byte pages. For example, if SRAM_BND is set to 10, then 5120 bytes of the SRAM will ...
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STAT0: Status0 Offset 030h STAT0 indicates the status of various Am79C976 func- tions. All bits in this register except for bits 12:10 indi- cate current status and are read only. Bits 12:10 are latches that indicate the cause of a ...
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Bit Name Link Status. This bit is set to the value of the Link Status bit in the status register (R1) of the default external PHY. (The default external PHY is the PHY addressed by the AP_PHY0_ADDR field of the ...
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SVID_A: PCI Subsystem Vendor ID Alias Register Offset 1B6h This register is a writable alias of the Subsystem Ven- dor ID field at offset 2Ch in PCI configuration space, which is read only. The purpose of this register is to ...
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VID_A: PCI Vendor ID Alias Register Offset 1B2h Table 82. VID_A: PCI Vendor ID Alias Register Bit Name Vendor ID. The PCI Vendor ID register is a 16-bit register that identifies the manufacturer of the Am79C976 controller. AMD’s Vendor ID ...
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Table 84. Bit Name Transmit Polling Interval. This register contains the time that the Am79C976 controller will wait between successive polling operations. The XMTPOLLTIME value is expressed as the two’s complement of the desired interval, where each bit of XMTPOLLTIME ...
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Control and Status Registers The Control and Status Registers (CSRs) are included for compatibility with older PCnet Family software. All CSR functions can be accessed more efficiently through the memory-mapped registers. The CSR space is accessible by performing accesses to ...
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INTR is read only. INTR is cleared by clearing all of the ac- tive individual interrupt bits that have not been masked out. 6 IENA Interrupt Enable allows INTA to be active if the Interrupt Flag is set. If IENA ...
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INIT is cleared by H_RESET, S_RESET set- ting the STOP bit. CSR1: Initialization Block Address 0 Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 IADR[15:0] Lower 16 bits of ...
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TINTM Transmit Interrupt TINTM is set, the TINT bit will be masked and unable to set the INTR bit. Read/Write accessible. TINTM is set by H_RESET but cleared by S_RESET and is not affected by STOP. 8 IDONM Initialization ...
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Read/Write accessible. The LAP- PEN bit will be reset H_RESET or S_RESET and will be unaffected by STOP. See Appendix B for more infor- ...
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RES Reserved Location. Written as zero and read as undefined. 12 TXDPOLL Disable Transmit Polling. If TXD- POLL is set, the Buffer Manage- ment Unit will disable transmit polling. Likewise, if TXDPOLL is cleared, automatic transmit poll- ing is ...
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RES Reserved locations. Written as zeros and read as undefined. CSR5: Extended Control and Interrupt 1 Certain bits in CSR5 indicate the cause of an interrupt. The register is designed so that these indicator bits are cleared by writing ...
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EXDINTE Obsolete function. Writing has no effect. Read as undefined. 5 MPPLBA Magic Packet Physical Logical Broadcast Accept. If MPPLBA is at its default value of 0, the Am79C976 controller will only de- tect a Magic Packet frame if ...
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The Am79C976 controller will contin the transmit and receive de- scriptor ring where it had left, when it entered the suspend mode. Read/Write accessible. SPND is cleared by S_RESET setting the ...
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De- scriptor. RDMD is cleared by H_RESET or RDMD is unaffected by setting the STOP bit. 12 CHDPOLL Disable Chain Polling. If CHD- POLL is set, the Buffer Manage- ment Unit will disable chain polling. ...
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S_RESET or setting the STOP bit. 6 MAPINTE MII Auto-Poll Interrupt Enable. If MAPINTE is set, the MAPINT bit will be able to set the INTR bit. Read/Write accessible. INTE is set H_RESET ...
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MIIPDTINTEMII PHY Detect Transition Inter- rupt Enable. If MIIPDTINTE is set to 1, the MIIPDTINT bit will be able to set the INTR bit. Read/Write DTINTE is set H_RESET and is not affected by S_RESET or ...
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Read/Write accessible. These bits are cleared by H_RESET but are unaffected by S_RESET, or STOP. CSR13: Physical Address Register 1 Note: Bits 15-0 in this register are programmable through ...
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DRTY Disable Retry. When DRTY is set to 1, the Am79C976 controller will attempt only one transmission. In this mode, the device will not pro- tect the first 64 bytes of frame data in the Transmit FIFO from being ...
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CSR24: Base Address of Receive Ring Lower Bit Name 31-16 RES 15-0 BADRL CSR25: Base Address of Receive Ring Upper Bit Name 31-16 RES 15-0 BADRU CSR26-29: Reserved ...
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Read/Write accessible. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR32-46: Reserved Bit Name Description 31-0 RES Reserved locations. Written as zeros and read as undefined. CSR47: Transmit Polling Interval Bit Name Description 31-16 RES Reserved locations. Written as ...
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Read/Write accessible. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR50-57: Reserved Bit Name Description 31-0 RES Reserved locations. Written as zeros and read as undefined. CSR58: Software Style This register is an ...
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Read/Write accessible. The SW- STYLE register will contain the value 00h following H_RESET and will be S_RESET or STOP. SWSTYLE Style [7:0] Name LANCE/ 00h PCnet-ISA controller 01h RES PCnet-PCI 02h controller PCnet-PCI 03h controller 04h VLAN 05h 64-bit Address ...
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CSR59-75: Reserved Bit Name Description 31-0 RES Reserved locations. Written as zeros and read as undefined. CSR76: Receive Ring Length Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 RCVRL Receive Ring Length. Contains ...
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Table 86. Receive Watermark Programming RCVFW[1:0] Bytes Received Read/Write RCVFW[1:0] is set to a value of 01b (64 bytes) after H_RESET or S_RESET and is unaffected by STOP. 11-10 XMTSP[1:0] Transmit Start Point. XMTSP controls the ...
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CSR81-87: Reserved Bit Name Description 31-0 RES Reserved locations. Written as zeros and read as undefined. CSR88: Chip ID Register Lower Bit Name Description 31-16 RES Reserved locations. Read as undefined. 15-12 PARTIDL Lower 4 bits of the Am79C976 controller ...
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RES Reserved locations. Written as zeros and read as undefined. CSR116: OnNow Power Mode Register Note: Bits 10-0 in this register are programmable through the EEPROM. Bit Name Description 31-11 RES Reserved locations. Written as zeros and read as ...
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S_RESET or setting the STOP bit. 3 RWU_DRIVER RWU Driver Type. If this bit is set to 1, RWU is a totem pole driver; otherwise RWU is an open drain output. Read/Write accessible. Cleared by H_RESET and is not ...
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IPG to 63h has the same effect as pro- gramming it to 60h. CAUTION: Use this parameter with care. By lowering the IPG below the IEEE 802.3 standard 96 bit times, the Am79C976 con- troller can interrupt normal ...
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Bus Configuration Registers The Bus Configuration Registers (BCRs) are included for compatibility with older PCnet Family software All BCR functions can be accessed more efficiently through the memory-mapped registers. BCRs are used to program the configuration of the bus interface ...
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SRAMSIZE 0000h 26 SRAMBND 0000h 27 Reserved 28 EBADDRL 29 EBADDRU 30 EBDR 31 STVAL FFFFh 32 MIICAS 0400h 33 MIIADDR 34 MIIMDR 35 PCIVID 1022h 36 PMC_A C802h 37 DATA0 0000h 38 DATA1 0000h 39 DATA2 0000h 40 ...