AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 97

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

SRAM Configuration
The Am79C976 controller uses external SSRAM for re-
ceive and transmit FIFOs. The size of the SSRAM can
be up to 4 Mbytes, organized as 1M X 32 bits. The size
of the SSRAM is indicated by the contents of the
SSRAM Size Register (or BCR25). SRAM_SIZE
should be loaded from the EEPROM.
The SSRAM is programmed in units of 512-byte pages.
To specify how much of the SSRAM is allocated to
transmit and how much is allocated to receive, the user
should program SRAM_BND Register (or BCR26, bits
15-0) with the page boundary where the receive buffer
begins. The SRAM_BND is also programmed in units
of 512-byte pages. The transmit buffer space starts at
0000h. It is up to the user or the software driver to split
up the memory for transmit or receive; there is no de-
faulted value. The minimum SSRAM size required is
four 512-byte pages for each transmit and receive
queue, which limits the SSRAM size to be at least 4
Kbytes.
The SRAM_BND upon H_RESET will be reset to
0000h. SRAM_BND must be programmed to a non-
zero value if the transmitter is enabled. SRAM_BND
should be programmed to a value larger than the max-
imum frame size to use the automatic retransmission
options, REX_UFLO, REX_RTRY, and RTRY_LCOL,
or if the transmit FIFO start point, XMTSP, is set to Full
Frame. (XMTSP is CTRL1, bits 17-16, or CSR80, bits
11-10.)
The Am79C976 controller does not allow software di-
agnostic access to the SRAM as do older devices in the
PCnet family. The Am79C976 controller provides soft-
ware access to an internal memory built-in self-test
(MBIST) controller which runs extensive, at-speed
9/14/00
ERA[19:0]
ROMCLK
ERD[7:0]
FLWE
FLOE
FLCS
Figure 39. Flash Write Sequence
P R E L I M I N A R Y
Am79C976
tests on the external SRAM, internal SRAM access
logic, and the PC board interconnect.
The MBIST controller can determine the size of the ex-
ternal SRAM and verify its operation using the following
procedure:
1. Program SRAM_SIZE to the minimum allowed
2. Write DM_START and DM_FAIL_STOP (write
3. Read DM_DONE (DATAMBIST bit 63) and
4. If DM_ERROR is set, the memory is defective; re-
5. Program SRAM_SIZE to the maximum value of
6. If DM_ERROR is zero, report the current value of
7. If DM_ERROR is set, program SRAM_SIZE to one-
8. Repeat, using the binary search algorithm, until the
EEPROM Interface
The Am79C976 device includes an interface to an op-
tional 16-bit word-oriented 93Cxx-compatible serial
EEPROM that supports automatic address increment-
ing (sequential read). This EEPROM can be used for
storing initial values for Am79C976 registers. The con-
tents of this EEPROM are automatically loaded into the
value of 4.
DATAMBIST bits 63:56 with 0x28). The remainder
of the DATAMBIST register ignores writes so it may
be written with arbitrary data or not written at all.
DM_ERROR (DATAMBIST bit 62) until DM_DONE
is set.
port the error and exit.
0x8000 and repeat steps 2 and 3.
SRAM_SIZE as the SSRAM size.
half the maximum (0x4000) and repeat steps 2
and 3.
SRAM size has been determined.
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