SLXT973QE Cortina Systems Inc, SLXT973QE Datasheet - Page 37

• Manufacturer Part Number: SLXT973QE
• Manufacturer: Cortina Systems Inc

Specifications of SLXT973QE

• Lead Free Status / RoHS Status: Not Compliant

LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
3.8.2
3.8.3
3.8.3.1
3.8.3.2
Cortina Systems
100BASE-X Protocol Sublayer Operations
In the seven-layer OSI communications model, the LXT973 Transceiver is a Physical
Layer 1 (PHY) device. The LXT973 Transceiver implements the Physical Coding Sublayer
(PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD)
sublayers of the reference model defined by the IEEE 802.3u specification. The following
paragraphs discuss the LXT973 Transceiver operation from the reference model point of
view.
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B
encoding/decoding function. For 100BASE-TX and 100BASE-FX operation, the PCS
layer provides IDLE symbols to the PMD-layer line driver as long as TXEN is de-asserted.
For 10BASE-T operation, the PCS layer merely provides a bus interface and serialization/
de-serialization function. 10BASE-T operation does not use the 4B/5B encoder.
Preamble Handling
When the MAC asserts TXEN, the PCS substitutes a /J/K/ symbol pair, also known as the
Start-of-Stream Delimiter (SSD), for the first two nibbles received across the MII. The PCS
layer continues to encode the remaining MII data until TXEN is de-asserted. It then
returns to supplying IDLE symbols to the line driver.
The PCS layer performs the opposite function in the receive direction by substituting two
preamble nibbles for the SSD.
Dribble Bits
The LXT973 Transceiver handles dribble bits in all modes. If one through four dribble bits
are received, the nibble is passed across the MII, and padded with ones if necessary. If
five through seven dribble bits are received, the second nibble is not sent to the MII bus.
®
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
3.8 100 Mbps Operation
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