WJLXT972MLC.A4 Q 911 Intel, WJLXT972MLC.A4 Q 911 Datasheet
WJLXT972MLC.A4 Q 911
Specifications of WJLXT972MLC.A4 Q 911
Related parts for WJLXT972MLC.A4 Q 911
WJLXT972MLC.A4 Q 911 Summary of contents
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... LXT972M Single-Port 10/100 Mbps PHY Transceiver ® The Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MACs) ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
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... Contents 1.0 Introduction to This Document ......................................................................................... 10 1.1 Document Overview ............................................................................................10 1.2 Related Documents............................................................................................. 10 2.0 Block Diagram for Intel 3.0 Pin Assignments for Intel 4.0 Signal Descriptions for Intel 5.0 Functional Description...................................................................................................... 21 5.1 Device Overview .................................................................................................22 5.1.1 Comprehensive Functionality ................................................................. 22 5.1.2 Optimal Signal Processing Architecture ................................................. 22 5.2 Network Media / Protocol Support ...
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... Top Label Markings............................................................................................. 91 11.0 Product Ordering Information ........................................................................................... 92 Figures ® 1 Intel LXT972M Transceiver Block Diagram....................................................... 11 2 Pin Assignments for Intel 3 Management Interface Read Frame Structure ................................................... 27 4 Management Interface Write Frame Structure ................................................... 27 5 Initialization Sequence for Intel 6 Link Establishment Overview) ............................................................................. 34 7 Clocking for 10BASE-T ...................................................................................... 37 8 Clocking for 100BASE-X ...
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... LXT972M Transceiver RESET_L Pulse Width and Recovery Timing .......74 34 PHY Identifier Bit Mapping ................................................................................. 78 ® 35 Intel LXT972M Transceiver LQFP Package Specifications............................... 90 36 Sample LQFP Package - Intel 37 Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel 91 38 Order Matrix for Intel Tables 1 Related Documents from Intel............................................................................. 10 ® 2 Intel LXT972M Transceiver Signal Types ......................................................... 13 ® ...
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... LXT972M Transceiver 10BASE-T Transmit Timing .................................. 68 ® 34 Intel LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing............... 69 ® 35 Intel LXT972M Transceiver 10BASE-T SQE (Heartbeat) Timing ..................... 70 ® 36 Intel LXT972M Transceiver Auto-Negotiation / Fast Link Pulse Timing ............ 71 ® 37 Intel LXT972M Transceiver MDIO Timing ......................................................... 72 ® 38 Intel LXT972M Transceiver Power-Up Timing .................................................. 73 ® ...
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... Block diagram changed. 11 Chapter 2.0, “Block Diagram for Intel® LXT972M Chapter 3.0, “Pin Assignments for Intel® LXT972M - Figure 2 “Pin Assignments for Intel® LXT972M Transceiver 48-Pin LQFP Package” - Figure 11 “Pin Assignments for Intel 12 figure for lead-free package. - Table 2 “Intel® LXT972M Transceiver Signal text changed ...
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... Table 50 “Register Set for Product-Specific Registers” Table 54 “LED Configuration Register - Address 20, Hex 14” - Table 56 “Transmit Control Register - Address 30, Hex 1E” Chapter 10.0, “Intel® LXT972M Transceiver Package 90 - Figure 35 “Intel® LXT972M Transceiver LQFP Package Specifications” Page 1 Text changed. 10 Figure 1 “Intel 21 Section 5.1, “Introduction” 22 Section 5.2.1.1, “ ...
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... Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 9 ...
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... This document includes the following subjects: • Chapter 2.0, “Block Diagram for Intel® LXT972M Transceiver” • Chapter 3.0, “Pin Assignments for Intel® LXT972M Transceiver” • Chapter 4.0, “Signal Descriptions for Intel • Chapter 5.0, “Functional Description” ...
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... Block Diagram for Intel Figure block diagram of the LXT972M Transceiver. (This block diagram is the same as the block diagram on the first page of this document. This copy of the block diagram appears here as a convenience to the reader.) ® Figure 1. Intel LXT972M Transceiver Block Diagram ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 3.0 Pin Assignments for Intel Figure 2 shows the pin assignments for the LXT972M Transceiver LQFP package. Figure 2. Pin Assignments for Intel VCCD 39 RX_CLK 40 RX_ER 41 TX_CLK 42 TX_EN 43 TXD0 44 TXD1 45 TXD2 46 TXD3 47 COL 48 Pin 1 12 ® ...
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... TPIP 18 TPIN 19 TDI 20 TDO 21 TMS 22 TCK 23 TRST_L 24 GND 25 GND Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Meaning Analog Input Analog Output Input Input/Output Output Open Drain Symbol Type – – – – – I ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver ® Table 3. Intel LXT972M Transceiver LQFP Numeric Pin List (Sheet Pin 26 LED/CFG3 27 LED/CFG2 28 LED/CFG1 29 VCCIO 30 GND 31 MDIO 32 MDC 33 RXD3 34 RXD2 35 RXD1 36 RXD0 37 RX_DV 38 GND 39 VCCD 40 RX_CLK 41 RX_ER 42 TX_CLK 43 TX_EN 44 TXD0 45 TXD1 46 TXD2 47 TXD3 ...
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... Table 6, “Intel® LXT972M Transceiver Network Interface Signal Descriptions” • Table 7, “Intel® LXT972M Transceiver Standard Bus and Interface Signal Descriptions” • Table 8, “Intel® LXT972M Transceiver Configuration and LED Driver Signal Descriptions” • Table 9, “Intel® LXT972M Transceiver Power, Ground, No-Connect Signal Descriptions” • ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 4 lists signal descriptions of the LXT972M Transceiver MII data interface pins. ® Table 4. Intel LXT972M Transceiver MII Data Interface Signal Descriptions LQFP Symbol Pin# 47 TXD3 46 TXD2 45 TXD1 44 TXD0 43 TX_EN 42 TX_CLK 33 RXD3 34 RXD2 35 RXD1 ...
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... Symbol Pin# 10 ADDR0 11 ADDR1 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Type Signal Description Management Data Clock. I Clock for the MDIO serial data channel. Maximum frequency is 8 MHz. Management Data Input/Output. I/O Bidirectional serial data channel for PHY/STA communication. ...
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... Configuration Register. (For details, see Configuration Register - Address 20, Hex 14” on page I/O Configuration Inputs 1-3. These pins also provide initial configuration settings. (For details, see Table 13, “Hardware Configuration Settings for Intel® LXT972M Transceiver” on page 33.) Section in the Functional Table 54, “LED 87.) Datasheet Document Number: 302875-005 ...
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... VCCIO 16 VCCA 39 VCCD Table 10 lists signal descriptions of LXT972M Transceiver Joint Test Action Group (JTAG) pins. Note JTAG port is not used, these pins do not need to be terminated. ® Table 10. Intel LXT972M Transceiver JTAG Test Signal Descriptions LQFP Symbol Pin# 19 TDI 20 TDO 21 TMS ...
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... LXT972M Transceiver. Note: • Driven High (Logic 1) • Driven Low (Logic 0) • High Impedance • Internal Pull-Down (Weak) ® Table 11. Intel LXT972M Transceiver Pin Types and Modes Modes RXD3:0 HWReset DL SFTPWRDN DL HZ with ISOLATE ID 20 ...
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... Section 5.7, “100 Mbps Operation” • Section 5.8, “10 Mbps Operation” • Section 5.9, “Monitoring Operations” • Section 5.10, “Boundary Scan (JTAG 1149.1) Functions” Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 21 ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.1 Device Overview The LXT972M Transceiver is a single-port Fast Ethernet 10/100 transceiver that supports 10 Mbps and 100 Mbps networks. It complies with applicable requirements of IEEE 802.3. It directly drives either a 100BASE-TX line or a 10BASE-T line. ...
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... Network Interface The network interface port consists of two differential signal pairs. For specific pin assignments, see Chapter 4.0, “Signal Descriptions for Intel® LXT972M The LXT972M Transceiver output drivers can generate one of the following outputs: • 100BASE-TX • ...
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... Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete this interface. On the transmit side, the LXT972M Transceiver has an active internal termination and does not require external termination resistors. Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings allow the designer to match the output waveform to the magnetic characteristics ...
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... MDIO Management Interface MDIO management interface topics include the following: • Section 5.2.3.1.1, “MDIO Addressing for Intel® LXT972M Transceiver” • Section 5.2.3.1.2, “MDIO Frame Structure” The LXT972M Transceiver supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver ® Table 12. Intel LXT972M Transceiver - PHY Device Address Selections ADDR1 ADDR0 (Pin 11) (Pin 10 PHY Device Address Selected Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ...
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... MDIO is not desired. The Hardware Control Interface uses the hardware configuration pins to set device configuration. For details, see page 33. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 4 (Read and Write). Chapter 7.0, “Electrical Specifications” ...
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... XI. The connection of a clock source to the XI pin requires the XO pin to be left open. To minimize transmit jitter, Intel recommends a crystal-based clock instead of a derived clock (that is, a PLL- based clock). A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a crystal, is frequently used in switch applications. For clock timing requirements, see Characteristics - REFCLK/XI and XO Pins” ...
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... Section 5.4.1, “MDIO Control Mode and Hardware Control Mode” • Section 5.4.2, “Reduced-Power Modes” • Section 5.4.3, “Reset for Intel® LXT972M Transceiver” • Section 5.4.4, “Hardware Configuration Settings” When the LXT972M Transceiver is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 5 shows the initialization sequence for the LXT972M Transceiver. The configuration bits may be set by the Hardware Control or MDIO interface. Figure 5. Initialization Sequence for Intel 30 ® LXT972M Transceiver Power-up or Reset Read H/W Control Interface ...
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... The MDIO registers remain accessible. 5.4.3 Reset for Intel The LXT972M Transceiver provides both hardware and software resets, each of which manage differently the configuration control of auto-negotiation, speed, and duplex-mode selection. For a software reset, Register bit 0. For register bit definitions used for software reset, see Table 41, “ ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver • During a software reset, bit settings in Address 4, Hex 4” on page 79 pins. Instead, the bit settings revert to the values that were read in during the last hardware reset. Therefore, any changes to pin values made since the last hardware reset are not detected during a software reset. • ...
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... Hardware Configuration Settings The LXT972M Transceiver provides a hardware option to set the initial device configuration. As listed in Table 13, the hardware option uses the hardware configuration pins, the settings for which provide control bits. Table 13. Hardware Configuration Settings for Intel Desired Mode Auto- Speed Duplex Neg. ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.5 Establishing Link Figure 6 shows an overview of link establishment for the LXT972M Transceiver. Note: When a link is established by parallel detection, the LXT972M Transceiver sets the duplex mode to half-duplex, as defined by the IEEE 802.3 standard. Figure 6. Link Establishment Overview) ...
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... Register 6 and assuming there is valid information in Registers 5 and 8. 5.5.1.3 Controlling Auto-Negotiation When auto-negotiation is controlled by software, Intel recommends the following steps: 1. After power-up, power-down, or reset, the power-down recovery time (specified in “Intel® LXT972M Transceiver RESET_L Pulse Width and Recovery Timing” on page must be exhausted before proceeding ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.6 MII Operation This section includes the following topics: • Section 5.6.1, “MII Clocks” • Section 5.6.2, “Transmit Enable” • Section 5.6.3, “Receive Data Valid” • Section 5.6.4, “Carrier Sense” ...
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... XI Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver show the clock cycles for each mode. 2.5 MHz during auto-negotiation and 10BASE-T Data & Idle 2.5 MHz during auto-negotiation and 10BASE-T Data & Idle Constant 25 MHz 2 ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 9. Clocking for Link Down Clock Transition RX_CLK TX_CLK 5.6.2 Transmit Enable The MAC must assert TX_EN the same time as the first nibble of preamble and de-assert TX_EN after the last nibble of the packet. ...
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... Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Test Operational Carrier Sense Loop- ...
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... Section 5.6.7.2, “Internal Digital Loopback (Test Loopback)” Figure 10 shows LXT972M Transceiver loopback paths. ® Figure 10. Intel LXT972M Transceiver Loopback Paths Intel® LXT972M Transceiver Operational MII Loopback 5.6.7.1 Operational Loopback • Operational loopback is provided for 10 Mbps half-duplex links when Register bit 16 ...
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... P1 P6 SFD Replaced by Start-of-Frame /J/K/ code-groups Delimiter (SFD) Start-of-Stream Delimiter (SSD) Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Destination and Source Packet Length Data Field Address (6 Octets each) (2 Octets) (Pad to minimum packet size ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver As shown in Figure 12, transmits the data to the network using MLT-3 line code. MLT-3 signals received from the network are de-scrambled, decoded, and sent across the MII to the MAC. Figure 12. 100BASE-TX Data Path Standard Data Flow ...
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... RX_ER. Figure 14. 100BASE-TX Reception with Invalid Symbol RX_CLK RX_DV RXD<3:0> preamble SFD SFD DA RX_ER Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver CRC 14, when the LXT972M Transceiver receives invalid symbols from the line ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.7.2 Collision Indication Figure 15 shows normal transmission. Figure 15. 100BASE-TX Transmission with No Errors TX_CLK TX_EN TXD<3:0> P CRS COL Upon detection of a collision, the COL output is asserted and remains asserted for the duration of the collision as shown in Figure 16 ...
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... Section 5.7.3.1, “Physical Coding Sublayer” • Section 5.7.3.2, “Physical Medium Attachment Sublayer” • Section 5.7.3.3, “Twisted-Pair Physical Medium Dependent Sublayer” Figure 17 shows the LXT972M Transceiver protocol sublayers. ® Figure 17. Intel LXT972M Protocol Sublayers PCS Sublayer PMA Sublayer PMD Sublayer ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.7.3.1 Physical Coding Sublayer The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/ decoding function. For 100BASE-TX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TX_EN is de-asserted. ...
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... The /J/ and /K/ (SSD) code groups are always sent in pairs, and /K/ follows /J/. 3. The /T/ and /R/ (ESD) code groups are always sent in pairs, and /R/ follows /T /H/ (Error) code group is used to signal an error condition. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 5B Code Name Start-of-Stream Delimiter (SSD), 2 ...
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... CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R. However, in this case RX_ER is asserted for one clock cycle when CRS is de-asserted. Intel does not recommend using CRS for Interframe Gap (IFG) timing for the following reasons: • ...
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... Address 30, Hex 1E” on page output waveform to match the characteristics of the magnetics. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 56, “Transmit Control Register - 89.) The slew-rate mechanism allows the designer to optimize the 49 ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.8 10 Mbps Operation The LXT972M Transceiver operates as a standard 10BASE-T transceiver and supports standard 10 Mbps functions. During 10BASE-T operation, the LXT972M Transceiver transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the LXT972M Transceiver drives link pulses onto the line ...
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... When polarity reversal is detected in 10BASE-T operation, register 17.5 is set to 1. (For details, see bit 17.5 in Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 26, “Intel® LXT972M Transceiver 69. Table 52, “Status Register #2 - Address 17, Hex 11” on page 85.) 51 ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.9 Monitoring Operations 5.9.1 Monitoring Auto-Negotiation Auto-negotiation can be monitored as follows: • Register bit 17.7 is set to ‘1’ once the auto-negotiation process is completed. • Register bits 1.2 and 17.10 are set to ‘1’ once the link is established. ...
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... Max current rating) as required by the hardware configuration. For details, see the discussion of Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 87) to indicate one of the following “Hardware Configuration Settings” on page (Table 54, “LED 33. ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 5.9.4 LED Pulse Stretching The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. The pulse stretch time is extended further if the event occurs again during this pulse stretch period. When an event such as receiving a packet occurs, the event is edge detected and it starts the stretch timer ...
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... Boundary Scan (JTAG 1149.1) Functions The LXT972M Transceiver includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. Note: For the related BSDL file, contact your local sales office or access the Intel website (www.intel.com). 5.10.1 Boundary Scan Interface The boundary scan interface consists of five pins (TMS, TDI, TDO, TRST_L, and TCK) ...
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... Table 18. Device ID Register for Intel Bits 31:28 Bits 27:12 Version Part ID (Hex) XXXX 1. The JEDEC 8-bit identifier. The MSB is for parity and is ignored. The Intel JEDEC (1111 1110), which becomes 111 1110. 56 Table 17 lists the four BSR modes of operation. Capture Shift Update ® ...
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... Table 20. I/O Pin Comparison of NIC and Switch RJ-45 Setups Symbol TPIP TPIN TPOP TPON Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Min Nom Max – – – – 0.0 ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 19 shows the LXT972M Transceiver in a typical twisted-pair interface, with the RJ-45 connections crossed over for a Switch configuration. ® Figure 19. Intel LXT972M Transceiver Typical Twisted-Pair Interface - Switch TPOP Intel® LXT972M Transceiver TPON VCCA 1 ...
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... Figure 20 shows the LXT972M Transceiver in a typical twisted-pair interface, with the RJ-45 connections configured for a NIC application. ® Figure 20. Intel LXT972M Transceiver Typical Twisted-Pair Interface - NIC Intel® LXT972M Transceiver 1. Center tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the center tap from a 2 ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Figure 21 shows a typical media independent interface (MII) for the LXT972M Transceiver. ® Figure 21. Intel LXT972M Transceiver Typical Media Independent Interface MAC 60 TX_EN TXD[3:0] TX_CLK RX_CLK Intel® LXT972M RX_DV RX_ER Transceiver RXD[3:0] CRS ...
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... Exceeding the absolute maximum rating values may cause permanent damage. • Functional operation under these conditions is not implied. • Exposure to maximum rating conditions for extended periods may affect device reliability. Table 21. Absolute Maximum Ratings for Intel Parameter Supply Voltage Storage Temperature Table 22 lists the recommended operating conditions for the LXT972M Transceiver ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 23 lists digital I/O characteristics for all pins except the MII, XI/XO, and LED/CFG pins. Table 23. Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins) Parameter Input Low voltage Input High voltage ...
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... Table 26. I/O Characteristics - LED/CFG Pins Parameter Input Low Voltage Input High Voltage Input Current Output Low Voltage Output High Voltage Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver 1 Symbol Min Typ V – – 2.0 – ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 27 lists the 100BASE-TX characteristics. Table 27. 100BASE-TX Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot/Undershoot Jitter (measured differentially) 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100 Ω ...
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... Timing Diagrams ® Figure 22. Intel LXT972M Transceiver 100BASE-TX Receive Timing TPI CRS RX_DV RXD[3:0] RX_CLK COL Note: Timing diagram depicts 4B mode. ® Table 30. Intel LXT972M Transceiver 100BASE-TX Receive Timing Parameters Parameter RXD[3:0], RX_DV, RX_ER RX_CLK High RXD[3:0], RX_DV, RX_ER hold ...
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... TXD[3:0] TPO CRS Note: Timing diagram depicts 4B mode. Figure 23 does not show the TX_ER signal. . ® Table 31. Intel LXT972M Transceiver 100BASE-TX Transmit Timing Parameters Parameter TXD[3:0], TX_EN setup to TX_CLK High TXD[3:0], TX_EN hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted ...
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... Figure 24. Intel LXT972M Transceiver 10BASE-T Receive Timing RX_CLK RXD, RX_DV, RX_ER CRS TPI COL ® Table 32. Intel LXT972M Transceiver 10BASE-T Receive Timing Parameter RXD, RX_DV. Setup to RX_CLK High. RXD, RX_DV, RX_ER Hold from RX_CLK High TPIP RXD out (Rx latency) CRS asserted to RXD, RX_DV, ...
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... LXT972M Transceiver 10BASE-T Transmit Timing TX_CLK TXD, TX_EN CRS TPO ® Table 33. Intel LXT972M Transceiver 10BASE-T Transmit Timing Parameter TXD, TX_EN, setup to TX_CLK High TXD, TX_EN, hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TPO out (Tx latency) 1. Typical values are at 25 ° ...
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... Figure 26. Intel LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing TX_EN TXD COL ® Table 34. Intel LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing Parameter Maximum transmit time Unjabber time 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing ...
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... LXT972M Transceiver 10BASE-T SQE (Heartbeat) Timing TX_CLK TX_EN COL ® Table 35. Intel LXT972M Transceiver 10BASE-T SQE (Heartbeat) Timing Parameter COL (SQE) Delay after TX_EN off COL (SQE) Pulse duration 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing ...
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... LXT972M Transceiver Auto-Negotiation and Fast Link Pulse Timing TPOP ® Figure 29. Intel LXT972M Transceiver Fast Link Pulse Timing TPOP ® Table 36. Intel LXT972M Transceiver Auto-Negotiation / Fast Link Pulse Timing Parameter Clock/Data pulse width Clock pulse to Data pulse Clock pulse to Clock pulse FLP burst width ...
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... LXT972M Transceiver MDIO Input Timing MDC MDIO ® Figure 31. Intel LXT972M Transceiver MDIO Output Timing MDC MDIO ® Table 37. Intel LXT972M Transceiver MDIO Timing Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, sourced by PHY MDC period 1. Typical values are at 25° ...
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... Figure 32. Intel LXT972M Transceiver Power-Up Timing VCC MDIO, and so on ® Table 38. Intel LXT972M Transceiver Power-Up Timing Parameter Voltage threshold 2 Power Up delay 1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production testing. ...
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... LXT972M Transceiver RESET_L Pulse Width and Recovery Timing RESET_L MDIO, and so on ® Table 39. Intel LXT972M Transceiver RESET_L Pulse Width and Recovery Timing Parameter RESET_L pulse width RESET_L recovery delay 1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production testing ...
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... Status Register Reserved 15 Extended Status Register Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 49 provide bit descriptions of the base registers (address 0 through 8), Register Name includes definitions of additional Bit Assignments See Table 41 See Table 42 ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 41 lists control register bits. Table 41. Control Register - Address 0, Hex 0 Bit Name 0.15 Reset 0.14 Loopback 0.13 Speed Selection Auto-Negotiation 0.12 Enable 0.11 Power-Down 0.10 Isolate Restart Auto- 0.9 Negotiation 0.8 Duplex Mode ...
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... RO = Read Only LL = Latching Low LH = Latching High Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Description 0 = PHY not able to perform 100BASE- PHY able to perform 100BASE- PHY not able to perform full-duplex 100BASE PHY able to perform full-duplex 100BASE-X ...
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... Figure 34. PHY Identifier Bit Mapping PHY ID Register #1 (Address 2) = 0013 Note: The Intel OUI is 00207B hex 78 44, see Figure 34. Description The PHY identifier is composed of bits 3 through 18 of the Organizationally Unique Identifier (OUI). Description The PHY identifier is composed of bits 19 through 24 of the OUI. ...
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... Some bits have their default values determined at reset by hardware configuration pins. For default details for these bits, see Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Description 0 = Port has no ability to send multiple pages Port has ability to send multiple pages. Ignore when read. ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 46 lists auto-negotiation link partner base page ability bits. Table 46. Auto-Negotiation Link Partner Base Page Ability Register - Address 5, Hex 5 Bit Name 5.15 Next Page 5.14 Acknowledge 5.13 Remote Fault 5.12 Reserved Asymmetric 5.11 Pause 5 ...
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... Able Read Only LH = Latching High Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Description Ignore when read. This bit indicates the status of the auto-negotiation variable base page. It flags synchronization with the auto-negotiation state diagram, allowing detection of interrupted links ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 48 lists auto-negotiation next page transmit bits. Table 48. Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7 Bit Name 7.15 Next Page (NP) 7.14 Reserved Message Page 7.13 (MP) Acknowledge 2 7.12 (ACK2) 7.11 Toggle (T) Message/ 7.10:0 Unformatted Code Field 1 ...
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... Reserved 29 Reserved 30 Transmit Control Register 31 Reserved Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Registers”.) Table 56 provide bit descriptions of the product-specific registers (address 17 Register Name Chapter 8.0, Bit Assignments See Table 51 See Table 52 ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 51 lists configuration bits. Table 51. Configuration Register - Address 16, Hex 10 Bit Name 16.15 Reserved 16.14 Force Link Pass 16.13 Transmit Disable Bypass Scrambler 16.12 (100BASE-TX) 16.11 Reserved Jabber 16.10 (10BASE-T) SQE 16.9 (10BASE-T) TP Loopback 16 ...
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... Reserved 17.0 Reserved Read Only. R/W = Read/Write Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Description Always LXT972M Transceiver is not operating 100BASE-TX mode LXT972M Transceiver is operating in 100BASE-TX mode LXT972M Transceiver is not transmitting a packet. ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 53 lists status change bits. Table 53. Status Change Register - Address 19, Hex 13 Bit Name 19.15:9 Reserved 19.8 Reserved 19.7 ANDONE 19.6 SPEEDCHG 19.5 DUPLEXCHG 19.4 LINKCHG 19.3 Reserved 19.2 Reserved 19.1 Reserved 19.0 Reserved 1 ...
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... Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Values are approximations. Not guaranteed or production tested. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Description 0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) ...
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... Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Table 54. LED Configuration Register - Address 20, Hex 14 (Sheet Bit Name LED3 20.7:4 Programming bits 20.3:2 LEDFREQ PULSE- 20.1 STRETCH 20.0 Reserved 1. R/W = Read /Write Read Only Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. ...
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... R/W = Read/Write 3. Latch State during Reset is based on the state of hardware configuration pins at RESET_L. Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 ® Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Description Write as ‘0’. Ignore on Read. Transmit Low Power 0 = Normal transmission Forces the transmitter into low power mode. ...
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... Intel LXT972M Transceiver Package Specifications ® Figure 35. Intel LXT972M Transceiver LQFP Package Specifications 48-Pin Low-Profile Quad Flat Pack Part Number LXT972M - Temperature Range (0ºC to +70ºC) NOTE: The package figure is generic and used only to demonstrate package dimensions. C0.55 (in MM ...
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... LQFP package for the LXT972M Transceiver. Note: In contrast to the Pb-Free (RoHS-compliant) LQFP package, the non-RoHS-compliant package does not have the “e3” symbol in the last line of the package label. Figure 36. Sample LQFP Package - Intel Pin 1 Figure 37 shows a sample Pb-Free (RoHS-compliant) LQFP package for the LXT972M Transceiver ...
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... Product Ordering Information Table 57 lists product ordering information for the LXT972M Transceiver. Table 57. Product Ordering Information Number DJLXT972MLC.A4 WJLXT972MLC.A4 Figure 38 shows an order matrix with sample information for ordering an LXT972M Transceiver. Figure 38. Order Matrix for Intel DJ 92 Package Revision Pin Count Type A4 LQFP ...