WJLXT972MLC.A4 Q 911 Intel, WJLXT972MLC.A4 Q 911 Datasheet - Page 37

• Manufacturer Part Number: WJLXT972MLC.A4 Q 911
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 Q 911

• Lead Free Status / RoHS Status: Compliant

5.6.1
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Figure 7. Clocking for 10BASE-T
Figure 8. Clocking for 100BASE-X
Note: The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The
MII Clocks
The LXT972M Transceiver is the master clock source for data transmission, and it supplies both
MII clocks (RX_CLK and TX_CLK). It automatically sets the clock speeds to match link
conditions.
Figure 7
LXT972M Transceiver samples these signals on the rising edge of TX_CLK.
TX_CLK
RX_CLK
XI
TX_CLK
RX_CLK
XI
•
•
When the link is operating at 100 Mbps, the clocks are set to 25 MHz.
When the link is operating at 10 Mbps, the clocks are set to 2.5 MHz.
through
Figure 9
show the clock cycles for each mode.
2.5 MHz during auto-negotiation
2.5 MHz during auto-negotiation
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
Intel
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Constant 25 MHz
Constant 25 MHz
25 MHz once 100BASE-X
25 MHz once 100BASE-X
Link Established
Link Established
B3391-01
B3390-01
37