PEB4265TV1.2T Infineon Technologies, PEB4265TV1.2T Datasheet - Page 315

• Manufacturer Part Number: PEB4265TV1.2T
• Manufacturer: Infineon Technologies

Specifications of PEB4265TV1.2T

• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 22
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary
6.3.4.2
An example with the same programming sequence as before, using the IOM-2 interface
is presented here to show the differences between the microcontroller interface and the
IOM-2 interface.
SOP Write to Channel 0 Starting After the Channel-Specific Read-Only Registers
Monitor
data down
10000001 10
10000001 10
01000100 11
01000100 10
00010101 11
00010101 10
00000000 11
00000000 10
00000000 11
00000000 10
00010001 11
00010001 10
00000000 11
00000000 10
11111111 11
11111111 11
Since the SLICOFI-2S/-2S2 has an open command structure, no fixed command length
is given. The IOM-2 handshake protocol allows for an infinite length of a data stream,
therefore the host has to terminate the data transfer by sending an end-of-message
signal (EOM) to the SLICOFI-2S/-2S2. The SLICOFI-2S/-2S2 will abort the transfer only
if the host tries to write or read beyond the allowed maximum offsets given by the
different types of commands. Each transfer has to start with the SLICOFI-2S/-2S2-
specific IOM-2 Address (81
Appending a command immediately to its predecessor without an EOM in between is not
allowed.
When reading interrupt registers, SLICOFI-2S/-2S2 stops the transfer after the fourth
register in IOM-2 mode. This is to prevent some host chips reading 16 bytes because
they can’t terminate the transfer after n bytes.
Data Sheet
MR/MX Monitor
IOM-2 Interface
data up
11111111 11
11111111 01
11111111 01
11111111 11
11111111 01
11111111 11
11111111 01
11111111 11
11111111 01
11111111 11
11111111 01
11111111 11
11111111 01
11111111 11
11111111 01
11111111 11
H
MR/MX Comment
) and must end with an EOM of the handshake bits.
SLICOFI-2x Command Structure and Programming
IOM-2 address first byte
IOM-2 address second byte
First command byte (SOP write for channel 0)
First command byte second time
Second command byte (offset to BCR1 register)
Second command byte second time
Contents of BCR1 register
Contents of BCR1 register second time
Contents of BCR2 register
Contents of BCR2 register second time
Contents of BCR3 register
Contents of BCR3 register second time
Contents of BCR4 register
Contents of BCR4 register second time
No more information (dummy byte)
Signaling EOM (end of message) by holding MX bit at ‘1’.
315
DuSLIC-S/-S2
2000-07-14