82V1671J IDT, Integrated Device Technology Inc, 82V1671J Datasheet - Page 78

• Manufacturer Part Number: 82V1671J
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1671J

• Number Of Channels: 4
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: PLCC
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Mounting: Surface Mount
• Operating Current: 95mA
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Lead Free Status / RoHS Status: Not Compliant

RSLIC & CODEC CHIPSET
LREG11: Debounce Filter Configuration, Read/Write (0AH/8AH)
LREG12: PCM Data Low Byte Register, Read Only (0BH)
LM_RECT
LM_TH[2:0]
DB[3:0]
This register is used for the master processor to monitor the transmit (A to D) PCM data. For linear code, the low byte of PCM data is
sent to this register before it is transmitted to the PCM Encoder in the transmit path. For compressed code, the total PCM data is sent to
this register before it is transmitted to the PCM Encoder in the transmit path.
DB_IO[3:0]
Command
Command
I/O data
I/O data
Enable the rectifier in the level meter.
LM_RECT = 0:
LM_RECT = 1:
Level meter threshold selection. If the absolute value of the level meter result exceeds the selected threshold, the
OTHRE bit will be set to 1.
LM_TH[2:0] = 000: Threshold is 0.0% (default);
LM_TH[2:0] = 001: Threshold is 12.5%;
LM_TH[2:0] = 010: Threshold is 25.0%;
LM_TH[2:0] = 011: Threshold is 37.5%;
LM_TH[2:0] = 100: Threshold is 50.0%;
LM_TH[2:0] = 101: Threshold is 62.5%;
LM_TH[2:0] = 110: Threshold is 75.0%;
LM_TH[2:0] = 111: Threshold is 87.5%.
Debounce interval selection for off-hook and ground-key detection. The debounce interval is programmable from 0.125
ms to 2 ms in steps of 0.125 ms, corresponding to the minimal debounce time of from 2 ms to 30 ms.
DB[3:0] = 0000:
DB[3:0] = 0001:
DB[3:0] = 0010:
DB[3:0] = 1110:
DB[3:0] = 1111:
(Note: During operating mode switching, there might be a narrow pulse of about 15 ms occurring on VTDC, resulting in
a false interrupt to be generated. If this happens, please set DB[3:0] to 0111B or above to filter this noise pulse.)
IO Pins debounce time selection (only effective for those IO pins used as digital inputs).The IO pins debounce time is
programmable from 2.5 ms to 32.5 ms in steps of 2 ms.
DB_IO[3:0] = 0000: the minimal debounce time is 2.5 ms (default);
DB_IO[3:0] = 0001: the minimal debounce time is 4.5 ms;
DB_IO[3:0] = 0010: the minimal debounce time is 6.5 ms;
DB_IO[3:0] = 1110: the minimal debounce time is 30.5 ms;
DB_IO[3:0] = 1111: the minimal debounce time is 32.5 ms.
R/W
b7
b7
0
...
...
...
...
b6
b6
0
0
The rectifier is disabled (default);
The rectifier is enabled.
the debounce interval is 0.125 ms, the minimal debounce time is 2 ms (default);
the debounce interval is 0.250 ms, the minimal debounce time is 4 ms;
the debounce interval is 0.375 ms, the minimal debounce time is 6 ms;
the debounce interval is 1.875 ms, the minimal debounce time is 30 ms;
the debounce interval is 2 ms, the minimal debounce time is 32 ms.
DB[3:0]
...
...
...
...
b5
b5
0
0
.
This register is used for MPI mode only.
78
b4
b4
0
0
PCM[7:0]
b3
b3
1
1
...
...
b2
b2
0
0
IDT82V1671/IDT82V1671A, IDT82V1074
DB_IO[3:0]
b1
b1
1
1
b0
b0
0
1