XCF02SVOG20C Xilinx Inc, XCF02SVOG20C Datasheet - Page 12

• Manufacturer Part Number: XCF02SVOG20C
• Description: PROM, PLATFORM FLASH, 2MBIT, 20TSSOP
• Manufacturer: Xilinx Inc

Specifications of XCF02SVOG20C

• Memory Type: Flash
• Memory Size: 2Mbit
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.3V To 2.7V, 3V To 3.6V
• Memory Case Style: TSSOP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°
• Programmable Type: In System Programmable
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Interface Type: Serial, Parallel, JTAG
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1287-5

Standby Mode
The PROM enters a low-power standby mode whenever CE is
deasserted (High). In standby mode, the address counter is
reset, CEO is driven High, and the remaining outputs are
placed in a high-impedance state regardless of the state of the
OE/RESET input. For the device to remain in the low-power
standby mode, the JTAG pins TMS, TDI, and TDO must not be
pulled Low, and TCK must be stopped (High or Low).
When using the FPGA DONE signal to drive the PROM CE
pin High to reduce standby power after configuration, an
external pull-up resistor should be used. Typically a 330Ω
Table 10: Truth Table for XCFxxS PROM Control Inputs
Table 11: Truth Table for XCFxxP PROM Control Inputs
DS123 (v2.18) May 19, 2010
Product Specification
Notes:
1.
2.
Notes:
1.
2.
3.
4.
5.
OE/RESET
OE/RESET
X = don’t care.
TC = Terminal Count = highest address value.
X = don’t care.
TC = Terminal Count = highest address value.
For the XCFxxP with Design Revisioning enabled, EA = end address (last address in the selected design revision).
For the XCFxxP with Design Revisioning enabled, Reset = address reset to the beginning address of the selected bank. If Design
Revisioning is not enabled, then Reset = address reset to address 0.
The BUSY input is only enabled when the XCFxxP is programmed for parallel data output and decompression is not enabled.
Control Inputs
High
High
High
High
Low
Low
X
X
(1)
R
Control Inputs
High
High
Low
Low
Low
Low
Low
Low
CE
CE
If address < TC
If address = TC
Held reset
Held reset
High
High
CF
↑
X
X
BUSY
High
Low
X
X
X
(2)
(2)
(1)
(5)
: increment
: don't change
If address < TC
address < EA
If address < TC
address = EA
Else
If address = TC
Unchanged
Reset
Held reset
Held reset
Internal Address
(4)
Internal Address
(4)
(4)
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMs
(3)
(3)
(2)
(2)
(2)
: increment
: don't change
and
and
: don't change
pull-up resistor is used, but refer to the appropriate FPGA
data sheet for the recommended DONE pin pull-up value. If
the DONE circuit is connected to an LED to indicate FPGA
configuration is complete, and is also connected to the
PROM CE pin to enable low-power standby mode, then an
external buffer should be used to drive the LED circuit to
ensure valid transitions on the PROM’s CE pin. If low-power
standby mode is not required for the PROM, then the CE pin
should be connected to ground.
Unchanged
Active and
High-Z
High-Z
High-Z
High-Z
Active
Active
DATA
High-Z
High-Z
High-Z
DATA
Active
CEO
High
High
High
High
High
High
Low
Outputs
CLKOUT
Outputs
High-Z
High-Z
High-Z
High-Z
Active
Active
Active
CEO
High
High
High
Low
Reduced
Reduced
Reduced
Standby
Standby
Active
Active
Active
Active
Active
Active
ICC
ICC
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