PIC18F46K80T-I/ML Microchip Technology, PIC18F46K80T-I/ML Datasheet - Page 210
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R](/photos/39/70/397090/qfn-44_sml.jpg)
PIC18F46K80T-I/ML
Manufacturer Part Number
PIC18F46K80T-I/ML
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F46K80T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F46K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F66K80 FAMILY
REGISTER 12-4:
TABLE 12-1:
DS39977C-page 210
MDCARH MDCHODIS
MDCARL
MDCON
MDSRC
PMD2
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used in the Data Signal Modulator mode.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
MDCLODIS
Name
R/W-0
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
MDCLODIS
MDSODIS
MDEN
Bit 7
MDCLODIS: Modulator Low Carrier Output Disable bit
1 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register)
0 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register)
MDCLPOL: Modulator Low Carrier Polarity Select bit
1 = Selected low carrier signal is inverted
0 = Selected low carrier signal is not inverted
MDCLSYNC: Modulator Low Carrier Synchronization Enable bit
1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high
0 = Modulator output is not synchronized to the low time carrier signal
Unimplemented: Read as ‘ 0 ’
MDCL<3:0> Modulator Data High Carrier Selection bits
1111 - 1001 = Reserved
1000 = CCP5 output (PWM Output mode only)
0111 = CCP4 output (PWM Output mode only)
0110 = CCP3 output (PWM Output mode only)
0101 = CCP2 output (PWM Output mode only)
0100 = ECCP1 output (PWM Output mode only)
0011 = Reference clock module signal
0010 = MDCIN2 port pin
0001 = MDCIN1 port pin
0000 = V
MDCLPOL
—
SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MOD
R/W-x
is disabled
is enabled
time carrier
MDCARL: MODULATION LOW CARRIER CONTROL REGISTER
SS
MDCHPOL
MDCLPOL
MDOE
Bit 6
W = Writable bit
‘1’ = Bit is set
MDCLSYNC
—
—
R/W-x
MDCHSYNC
MDCLSYNC
MDSLR
Bit 5
—
—
U-0
Preliminary
—
MDOPOL
Bit 4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
—
—
—
—
MDCL3
R/W-x
(1)
MDSRC3
MODMD
MDCH3
MDCL3
MDO
Bit 3
(1)
MDCL2
R/W-x
ECANMD
MDSRC2
MDCH2
MDCL2
(1)
Bit 2
—
(1)
2011 Microchip Technology Inc.
x = Bit is unknown
MDCL1
R/W-x
CMP2MD
MDSRC1
MDCH1
MDCL1
Bit 1
—
(1)
MDCL0
CMP1MD
MDSRC0
MDCH0
MDCL0
R/W-x
MDBIT
Bit 0
bit 0
(1)
E
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