PIC18F46K80T-I/ML Microchip Technology, PIC18F46K80T-I/ML Datasheet - Page 374
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R](/photos/39/70/397090/qfn-44_sml.jpg)
PIC18F46K80T-I/ML
Manufacturer Part Number
PIC18F46K80T-I/ML
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F46K80T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F46K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F66K80 FAMILY
23.7
Figure 23-6
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 23-7
after the GO/DONE bit has been set, the ACQT<2:0>
bits set to ‘ 010 ’ and a 4 T
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
FIGURE 23-6:
FIGURE 23-7:
DS39977C-page 374
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
1
conversion
A/D Conversions
T
T
Set GO/DONE bit
CY
Automatic
Acquisition
Time
ACQT
Holding capacitor is disconnected from analog input (typically 100 ns)
shows the operation of the A/D Converter
shows the operation of the A/D Converter
2
- T
AD
Cycles
Conversion starts
T
3
AD
sample.
A/D CONVERSION T
A/D CONVERSION T
1 T
AD
4
b11
AD
acquisition time selected.
2 T
Conversion starts
(Holding capacitor is disconnected)
1
This
b10
AD
3 T
b11
2
AD
means
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
b9
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
4 T
b10
AD
AD
3
AD
b8
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
5 T
Preliminary
ADIF bit is set, holding capacitor is reconnected to analog input.
the
ADIF bit is set, holding capacitor is connected to analog input.
b9
4
AD
b7
6 T
T
5
b8
AD
AD
b6
7 T
Cycles
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
started. After this wait, acquisition on the selected
channel is automatically started.
Note:
b7
AD
6
AD
b5
wait is required before the next acquisition can be
8
b6
T
7
AD
b4
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
9 T
b5
8
AD
b3
10
ACQ
ACQ
T
b4
9
AD
2011 Microchip Technology Inc.
b2
= 0)
= 4 T
11
T
10
b3
AD
AD
b1
12
)
T
b2
11
AD
b0
13
12
b1
13
b0
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