PIC18F46K80T-I/ML Microchip Technology, PIC18F46K80T-I/ML Datasheet - Page 454
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PIC18F46K80T-I/ML
Manufacturer Part Number
PIC18F46K80T-I/ML
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F46K80T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F46K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F66K80 FAMILY
27.10 Synchronization
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time
(Sync_Seg). The circuit will then adjust the values of
Phase Segment 1 and Phase Segment 2 as necessary.
There are two mechanisms used for synchronization.
27.10.1
Hard synchronization is only done when there is a
recessive to dominant edge during a bus Idle condition,
indicating the start of a message. After hard synchroni-
zation, the bit time counters are restarted with
Sync_Seg. Hard synchronization forces the edge,
which has occurred to lie within the synchronization
segment of the restarted bit time. Due to the rules of
synchronization, if a hard synchronization occurs, there
will not be a resynchronization within that bit time.
27.10.2
As a result of resynchronization, Phase Segment 1
may be lengthened or Phase Segment 2 may be short-
ened. The amount of lengthening or shortening of the
phase buffer segments has an upper bound given by
the Synchronization Jump Width (SJW). The value of
the SJW will be added to Phase Segment 1 (see
Figure
Figure
and 4 T
Clocking information will only be derived from reces-
sive to dominant transitions. The property, that only a
fixed maximum number of successive bits have the
same value, ensures resynchronization to the bit
stream during a frame.
FIGURE 27-6:
DS39977C-page 454
Input
Signal
Bit
Time
Segments
T
Q
27-6) or subtracted from Phase Segment 2 (see
27-7). The SJW is programmable between 1 T
Q
.
HARD SYNCHRONIZATION
RESYNCHRONIZATION
Sync
LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1)
Segment
Prop
Nominal Bit Length
Segment 1
Phase
Preliminary
Q
Actual Bit Length
The phase error of an edge is given by the position of
the edge relative to Sync_Seg, measured in T
phase error is defined in magnitude of T
• e = 0 if the edge lies within Sync_Seg.
• e > 0 if the edge lies before the sample point.
• e < 0 if the edge lies after the sample point of the
If the magnitude of the phase error is less than, or equal
to, the programmed value of the Synchronization Jump
Width, the effect of a resynchronization is the same as
that of a hard synchronization.
If the magnitude of the phase error is larger than the
Synchronization Jump Width and if the phase error is
positive, then Phase Segment 1 is lengthened by an
amount equal to the Synchronization Jump Width.
If the magnitude of the phase error is larger than the
resynchronization jump width and if the phase error is
negative, then Phase Segment 2 is shortened by an
amount equal to the Synchronization Jump Width.
27.10.3
• Only one synchronization within one bit time is
• An edge will be used for synchronization only if
• All other recessive to dominant edges fulfilling
SJW
previous bit.
allowed.
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
rules 1 and 2 will be used for resynchronization,
with the exception that a node transmitting a
dominant bit will not perform a resynchronization
as a result of a recessive to dominant edge with a
positive phase error.
Sample Point
SYNCHRONIZATION RULES
2011 Microchip Technology Inc.
Segment 2
Phase
Q
as follows:
Q
. The
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