PIC24F04KA201T-I/SS Microchip Technology, PIC24F04KA201T-I/SS Datasheet - Page 106
![PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC24F04KA201T-I/SS
Manufacturer Part Number
PIC24F04KA201T-I/SS
Description
PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24F04KA201-ISS.pdf
(8 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F04KA201-ISS.pdf
(224 pages)
4.PIC24F04KA201-ISS.pdf
(26 pages)
Specifications of PIC24F04KA201T-I/SS
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (1.375K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC24F04KA201-ISS PDF datasheet
- PIC24F04KA201-ISS PDF datasheet #2
- PIC24F04KA201-ISS PDF datasheet #3
- PIC24F04KA201-ISS PDF datasheet #4
- Current page: 106 of 224
- Download datasheet (4Mb)
PIC24F04KA201 FAMILY
FIGURE 12-1:
DS39937B-page 104
Note 1:
T2CK
Set T3IF
ADC Event Trigger
Data Bus<15:0>
The 32-Bit Timer Configuration (T32) bit must be set for 32-bit timer/counter operation. All control bits
are respective to the T2CON register.
TGATE
TIMER2/3 (32-BIT) BLOCK DIAGRAM
1
0
Read TMR2
Write TMR2
Reset
Equal
MSB
(1)
(1)
16
TMR3HLD
16
TMR3
PR3
16
Comparator
Preliminary
Q
Q
Gate
Sync
T
CY
CK
16
TMR2
D
PR2
LSB
1x
00
01
TON
Sync
TGATE
TCS
© 2009 Microchip Technology Inc.
TCKPS<1:0>
1, 8, 64, 256
Prescaler
2
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