PIC24F04KA201T-I/SS Microchip Technology, PIC24F04KA201T-I/SS Datasheet - Page 134
![PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC24F04KA201T-I/SS
Manufacturer Part Number
PIC24F04KA201T-I/SS
Description
PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24F04KA201-ISS.pdf
(8 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F04KA201-ISS.pdf
(224 pages)
4.PIC24F04KA201-ISS.pdf
(26 pages)
Specifications of PIC24F04KA201T-I/SS
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (1.375K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC24F04KA201-ISS PDF datasheet
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PIC24F04KA201 FAMILY
REGISTER 16-3:
REGISTER 16-4:
DS39937B-page 132
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-10
bit 9-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-5
bit 4
bit 2-0
Note 1:
AMSK7
R/W-0
U-0
U-0
U-0
—
—
—
2:
To enable the actual OC1 output, the OCPWM1 module has to be enabled.
Bit 3 is described in related chapters.
Unimplemented: Read as ‘0’
SMBUSDEL: SMBus SDA Input Delay Select bit
1 = The I
0 = The 1
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
AMSK<9:0>: Mask for Address Bit x Select bits
1 = Enable masking for bit x of incoming message address; bit match not required in this position
0 = Disable masking for bit x; bit match required in this position
AMSK6
U-0
U-0
R/W-0
—
—
U-0
—
I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER
PADCFG1: PAD CONFIGURATION CONTROL REGISTER
2
2
C™ module is configured for a longer SMBus input delay (nominal 300 ns delay)
C module is configured for a legacy input delay (nominal 150 ns delay)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
AMSK5
R/W-0
U-0
—
SMBUSDEL
R/W-0
U-0
—
AMSK4
R/W-0
U-0
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
OC1TRIS
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
AMSK3
R/W-0
U-0
—
(1,2)
AMSK2
R/W-0
U-0
U-0
—
—
U-0
—
© 2009 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
AMSK9
AMSK1
R/W-0
R/W-0
U-0
U-0
—
—
AMSK8
AMSK0
R/W-0
R/W-0
U-0
U-0
—
—
bit 8
bit 0
bit 8
bit 0
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