PIC24F04KA201T-I/SS Microchip Technology, PIC24F04KA201T-I/SS Datasheet - Page 30
![PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC24F04KA201T-I/SS
Manufacturer Part Number
PIC24F04KA201T-I/SS
Description
PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24F04KA201-ISS.pdf
(8 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F04KA201-ISS.pdf
(224 pages)
4.PIC24F04KA201-ISS.pdf
(26 pages)
Specifications of PIC24F04KA201T-I/SS
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (1.375K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC24F04KA201 FAMILY
4.2.2
To maintain backward compatibility with PIC
and improve data space memory usage efficiency, the
PIC24F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
EA calculations are internally scaled to step through
word-aligned memory. For example, the core recog-
nizes that Post-Modified Register Indirect Addressing
mode [Ws++] will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Data byte reads will read the complete word, which
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, the data
memory and the registers are organized as two
parallel, byte-wide entities with shared (word) address
decode but separate write lines. Data byte writes only
write to the corresponding side of the array or register,
which matches the byte address.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a mis-
aligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed, but the write
will not occur. In either case, a trap is then executed,
allowing the system and/or user to examine the
machine state prior to execution of the address Fault.
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A sign-extend instruction (SE) is provided to allow the
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
TABLE 4-2:
DS39937B-page 28
Legend: — = No implemented SFRs in this block.
000h
100h
200h
300h
400h
500h
600h
700h
DATA MEMORY ORGANIZATION
AND ALIGNMENT
I
xx00
2
IMPLEMENTED REGIONS OF SFR DATA SPACE
C™
—
—
—
—
ADC/CMTU
Timers
UART
Comp
xx20
—
—
—
Core
System/DS/HLVD
®
devices
Capture
SFR Space Address
xx40
—
—
—
—
Preliminary
SPI
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.
4.2.3
The 8-Kbyte area between 0000h and 1FFFh is
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions. The
remainder of the data space is addressable indirectly.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing (MDA) with a 16-bit address field. For
PIC24F04KA201
implemented data memory lies in Near Data Space
(NDS).
4.2.4
The first 2 Kbytes of the near data space, from 0000h
to 07FFh, are primarily occupied with Special Function
Registers (SFRs). These are used by the PIC24F core
and peripheral modules for controlling the operation of
the device.
SFRs are distributed among the modules that they
control and are generally grouped together by that
module. Much of the SFR space contains unused
addresses; these are read as ‘0’. The SFR space,
where the SFRs are actually implemented, is provided
in Table 4-2. Each implemented area indicates a
32-byte region where at least one address is
implemented as an SFR. A complete listing of
implemented SFRs, including their addresses, is
provided in Table 4-3 through Table 4-21.
NVM/PMD
xx60
ICN
—
—
—
—
—
NEAR DATA SPACE
SFR SPACE
Compare
xx80
—
—
—
—
—
family
© 2009 Microchip Technology Inc.
Interrupts
xxA0
—
—
—
—
—
—
devices,
—
xxC0
—
—
—
—
—
the
I/O
xxE0
—
—
—
—
—
—
entire
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