PIC24F04KA201T-I/SS Microchip Technology, PIC24F04KA201T-I/SS Datasheet - Page 94
![PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC24F04KA201T-I/SS
Manufacturer Part Number
PIC24F04KA201T-I/SS
Description
PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24F04KA201-ISS.pdf
(8 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F04KA201-ISS.pdf
(224 pages)
4.PIC24F04KA201-ISS.pdf
(26 pages)
Specifications of PIC24F04KA201T-I/SS
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (1.375K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC24F04KA201 FAMILY
9.2.2
Idle mode has these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
• If the WDT or FSCM is enabled, the LPRC will
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle, the clock is reapplied to the CPU
and instruction execution begins immediately, starting
with the instruction following the PWRSAV instruction or
the first instruction in the ISR.
9.2.3
Any interrupt that coincides with the execution of a
PWRSAV instruction will be held off until entry into Sleep
or Idle mode has completed. The device will then
wake-up from Sleep or Idle mode.
9.2.4
In PIC24F04KA201 family devices, Deep Sleep mode
is intended to provide the lowest levels of power
consumption available, without requiring the use of
external switches to completely remove all power from
the device. Entry into Deep Sleep mode is completely
under software control. Exit from Deep Sleep mode can
be triggered from any of the following events:
• POR event
• MCLR event
• External Interrupt 0
• Deep Sleep Watchdog Timer (DSWDT) time-out
The device has a dedicated Deep Sleep Brown-out
Reset (DSBOR) and a Deep Sleep Watchdog Timer
Reset (DSWDT) for monitoring voltage and time-out
events. The DSBOR and DSWDT are independent of
the standard BOR and WDT used with other
power-managed modes (Sleep, Idle and Doze).
DS39937B-page 92
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 9.4
“Selective Peripheral Module Control”).
also remain active.
IDLE MODE
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
DEEP SLEEP MODE
Preliminary
9.2.4.1
Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register, and then executing a SLEEP
instruction (PWRSAV #SLEEP_MODE) within one instruc-
tion cycle to minimize the chance that Deep Sleep will
be spuriously entered.
If the PWRSAV command is not given within one instruc-
tion cycle, the DSEN bit will be cleared by the hardware
and must be set again by the software before entering
Deep Sleep mode. The DSEN bit is also automatically
cleared when exiting the Deep Sleep mode.
The sequence to enter Deep Sleep mode is:
1.
2.
3.
4.
5.
Any time the DSEN bit is set, all bits in the DSWSRC
register will be automatically cleared.
9.2.4.2
Deep Sleep mode exits on any one of the following events:
• POR event on V
• DSWDT time-out. When the DSWDT timer times
• Assertion (‘0’) of the MCLR pin.
• Assertion of the INT0 pin (if the interrupt was
circuit to re-arm the V
external V
natural arming voltage of the POR circuit.
out, the device exits Deep Sleep.
enabled before Deep Sleep mode was entered).
The polarity configuration is used to determine the
assertion level (‘0’ or ‘1’) of the pin that will cause
an exit from Deep Sleep mode. Exiting from Deep
Sleep mode requires a change on the INT0 pin
while in Deep Sleep mode.
Note:
If the application requires the Deep Sleep WDT,
enable it and configure its clock source (see
Section 9.2.4.5
details).
If the application requires Deep Sleep BOR,
enable it by programming the DSBOREN
Configuration bit (FDS<6>).
If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).
Enable Deep Sleep mode by setting the DSEN
bit (DSCON<15>).
Enter Deep Sleep mode by issuing 3 NOP
commands and then a PWRSAV #0 instruction.
To re-enter Deep Sleep after a Deep Sleep
wake-up, allow a delay of at least 3 T
after clearing the RELEASE bit.
DD
Entering Deep Sleep Mode
Exiting Deep Sleep Mode
supply must be lowered to the
DD
supply. If there is no DSBOR
“Deep
DD
© 2009 Microchip Technology Inc.
supply POR circuit, the
Sleep
WDT”
for
CY
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