PIC24F08KA102-E/ML Microchip Technology, PIC24F08KA102-E/ML Datasheet - Page 131
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PIC24F08KA102-E/ML
Manufacturer Part Number
PIC24F08KA102-E/ML
Description
8KB Flash, 1.5KB RAM, 512B EEPROM, 16 MIPS, 24 I/O,16-bit PIC24F Family, NanoWat
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet
1.MA240017.pdf
(254 pages)
Specifications of PIC24F08KA102-E/ML
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (2.75K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC24F
Core
PIC
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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To set up the SPI module for the Enhanced Buffer
Master (EBM) mode of operation:
1.
2.
3.
4.
5.
6.
FIGURE 16-2:
© 2009 Microchip Technology Inc.
SS1/FSYNC1
If using interrupts:
a)
b)
c)
Write the desired settings to the SPI1CON1
and SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 1.
Clear the SPIROV bit (SPI1STAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
Write the data to be transmitted to the SPI1BUF
register. Transmission (and reception) will start
as soon as data is written to the SPI1BUF
register.
SDO1
SCK1
SDI1
Clear the respective SPI1IF bit in the IFS0
register.
Set the respective SPI1IE bit in the IEC0
register.
Write the respective SPI1IPx bits in the
IPC2 register.
Read SPI1BUF
Control
Transfer
Sync
SPI1 MODULE BLOCK DIAGRAM (ENHANCED BUFFER MODE)
Receive Buffer
8-Level FIFO
bit 0
Control
SPI1SR
Clock
SPI1BUF
Shift Control
Transmit Buffer
8-Level FIFO
Preliminary
Transfer
Write SPI1BUF
PIC24F16KA102 FAMILY
Select
Edge
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
8.
16
Clear the SPI1BUF register.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPI1CON1 and
SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 0.
Clear the SMP bit.
If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SS1 pin.
Clear the SPIROV bit (SPI1STAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
Secondary
1:1 to 1:8
Prescaler
Clear the respective SPI1IF bit in the IFS0
register.
Set the respective SPI1IE bit in the IEC0
register.
Write the respective SPI1IPx bits in the
IPC2 register to set the interrupt priority.
Internal Data Bus
1:1/4/16/64
Prescaler
Primary
DS39927B-page 129
SPI1CON1<1:0>
SPI1CON1<4:2>
Enable
Master Clock
F
CY
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