PIC24F08KA102-E/ML Microchip Technology, PIC24F08KA102-E/ML Datasheet - Page 142
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PIC24F08KA102-E/ML
Manufacturer Part Number
PIC24F08KA102-E/ML
Description
8KB Flash, 1.5KB RAM, 512B EEPROM, 16 MIPS, 24 I/O,16-bit PIC24F Family, NanoWat
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet
1.MA240017.pdf
(254 pages)
Specifications of PIC24F08KA102-E/ML
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (2.75K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC24F
Core
PIC
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC24F16KA102 FAMILY
REGISTER 17-2:
DS39927B-page 140
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
ACKSTAT
R/C-0, HS R/C-0, HS
R-0, HSC
IWCOL
ACKSTAT: Acknowledge Status bit
1 = NACK was detected last
0 = ACK was detected last
Hardware set or clear at end of Acknowledge.
TRSTAT: Transmit Status bit
(When operating as I
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at beginning of master transmission; hardware clear at end of slave Acknowledge.
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when address matches general call address; hardware clear at Stop detection.
ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at match of 2
IWCOL: Write Collision Detect bit
1 = An attempt to write to the I2C1TRN register failed because the I
0 = No collision
Hardware set at occurrence of write to I2C1TRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2C1RCV register is still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2C1RSR to I2C1RCV (cleared by software).
D/A: Data/Address bit (when operating as I
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was the device address
Hardware clear at device address match; hardware set by write to I2C1TRN or by reception of slave byte.
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
R-0, HSC
TRSTAT
I2COV
I2C1STAT: I2C1 STATUS REGISTER
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R-0, HSC
U-0
D/A
—
2
C™ master; applicable to master transmit operation.)
R/C-0, HSC R/C-0, HSC
nd
U-0
byte of matched 10-bit address; hardware clear at Stop detection.
—
P
Preliminary
HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
2
U-0
—
C slave)
S
R/C-0, HS
R-0, HSC
BCL
R/W
x = Bit is unknown
2
C module is busy
R-0, HSC
R-0, HSC
GCSTAT
RBF
© 2009 Microchip Technology Inc.
R-0, HSC
R-0, HSC
ADD10
TBF
bit 8
bit 0
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