PIC24F08KA102-E/ML Microchip Technology, PIC24F08KA102-E/ML Datasheet - Page 139
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PIC24F08KA102-E/ML
Manufacturer Part Number
PIC24F08KA102-E/ML
Description
8KB Flash, 1.5KB RAM, 512B EEPROM, 16 MIPS, 24 I/O,16-bit PIC24F Family, NanoWat
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet
1.MA240017.pdf
(254 pages)
Specifications of PIC24F08KA102-E/ML
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (2.75K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC24F
Core
PIC
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17.3
To compute the Baud Rate Generator (BRG) reload
value, use Equation 17-1.
EQUATION 17-1:
TABLE 17-1:
TABLE 17-2:
© 2009 Microchip Technology Inc.
Note 1:
Note 1:
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
1111 1xx
1111 0xx
Note 1: Based on F
Address
Slave
2:
3:
Required
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
System
F
or
I2C1BRG
Setting Baud Rate When
Operating as a Bus Master
1 MHz
1 MHz
1 MHz
SCL
F
The address bits listed here will never cause an address match, independent of the address mask settings.
Address will be Acknowledged only if GCEN = 1.
Match on this address can only occur on the upper byte in 10-Bit Addressing mode.
SCL
Based on F
PLL are disabled.
=
--------------------------------------------------------------------- -
I2C1BRG
R/W
Bit
I
I
0
1
x
x
x
x
x
x
2
2
=
C™ CLOCK RATES
C™ RESERVED ADDRESSES
⎛
⎝
COMPUTING BAUD RATE
RELOAD VALUE
----------- -
F
F
CY
CY
SCL
CY
General Call Address
Start Byte
Cbus Address
Reserved
Reserved
HS Mode Master Code
Reserved
10-Bit Slave Upper Byte
= F
= F
+ +
–
F
1
----------------------------- -
10 000 000
OSC
CY
OSC
,
----------------------------- -
10 000 000
16 MHz
16 MHz
16 MHz
F
8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
8 MHz
4 MHz
/2, Doze mode and
/2, Doze mode and PLL are disabled.
,
CY
F
F
CY
,
CY
,
⎞
⎠
(1)
–
(1)
1
(2)
(3)
Preliminary
(Decimal)
PIC24F16KA102 FAMILY
(1)
157
78
39
37
18
13
9
4
6
3
I2C1BRG Value
17.4
The I2C1MSK register (Register 17-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit
location (= 1) in the I2C1MSK register causes the slave
module to respond whether the corresponding address
bit value is ‘0’ or ‘1’. For example, when I2C1MSK is set
to ‘00100000’, the slave module will detect both
addresses: ‘0000000’ and ‘00100000’.
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the IPMIEN bit (I2C1CON<11>).
Description
Note:
(Hexadecimal)
Slave Address Masking
As a result of changes in the I
the addresses in Table 17-2 are reserved
and will not be Acknowledged in Slave
mode. This includes any address mask
settings
addresses.
9D
4E
27
25
12
D
9
4
6
3
that
include
1.026 MHz
1.026 MHz
0.909 MHz
DS39927B-page 137
100 kHz
100 kHz
404 kHz
404 kHz
385 kHz
385 kHz
Actual
99 kHz
F
any
SCL
2
C protocol,
of
these
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