PIC24F08KA102-E/ML Microchip Technology, PIC24F08KA102-E/ML Datasheet - Page 176
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PIC24F08KA102-E/ML
Manufacturer Part Number
PIC24F08KA102-E/ML
Description
8KB Flash, 1.5KB RAM, 512B EEPROM, 16 MIPS, 24 I/O,16-bit PIC24F Family, NanoWat
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet
1.MA240017.pdf
(254 pages)
Specifications of PIC24F08KA102-E/ML
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (2.75K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC24F
Core
PIC
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC24F16KA102 FAMILY
-
REGISTER 22-4:
DS39927B-page 174
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-12
bit 11-8
bit 7
bit 6-5
bit 4-0
CH0NB
CH0NA
R/W-0
R/W-0
CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is V
Unimplemented: Read as ‘0’
CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits
1111 = Channel 0 positive input is band gap reference (V
1110 = Channel 0 positive input is band gap, divided by two, reference (V
1101 = No channels connected (actual ADC MUX switch activates but input floats); used for CTMU
1100 = Channel 0 positive input is AN12
1011 = Channel 0 positive input is AN11
1010 = Channel 0 positive input is AN10
1001 = Reserved
1000 = Reserved
0110 = AV
0110 = AV
0101 = Channel 0 positive input is AN5
0100 = Channel 0 positive input is AN4
0010 = Channel 0 positive input is AN3
0010 = Channel 0 positive input is AN2
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is V
Unimplemented: Read as ‘0’
CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits
1111 = Channel 0 positive input is band gap reference (V
1110 = Channel 0 positive input is band gap, divided by two, reference (V
1101 = No channels connected (actual ADC MUX switch activates but input floats); used for CTMU
1100 = Channel 0 positive input is AN12
1011 = Channel 0 positive input is AN11
1010 = Channel 0 positive input is AN10
1001 = Reserved
1000 = Reserved
0110 = AV
0110 = AV
0101 = Channel 0 positive input is AN5
0100 = Channel 0 positive input is AN4
0010 = Channel 0 positive input is AN3
0010 = Channel 0 positive input is AN2
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
U-0
U-0
—
—
AD1CHS: A/D INPUT SELECT REGISTER
DD
SS
DD
SS
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
CH0SA4
R/W-0
R
R
U-0
-
-
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CH0SB3
CH0SA3
R/W-0
R/W-0
BG
BG
)
)
CH0SB2
CH0SA2
R/W-0
R/W-0
© 2009 Microchip Technology Inc.
x = Bit is unknown
BG
BG
CH0SB1
CH0SA1
/2)
/2)
R/W-0
R/W-0
CH0SB0
CH0SA0
R/W-0
R/W-0
bit 8
bit 0
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