USB3320C-EZK-TR Standard Microsystems (SMSC), USB3320C-EZK-TR Datasheet - Page 28

• Manufacturer Part Number: USB3320C-EZK-TR
• Manufacturer: Standard Microsystems (SMSC)

Specifications of USB3320C-EZK-TR

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

Revision 1.0 (07-14-09)
5.4.2
Figure 5.5 Example of Circuit Used to Shift a Reference Clock Common-mode Voltage Level
After the PLL has locked to the correct frequency, the USB3320 generates the 60MHz ULPI clock on
the CLKOUT pin, and de-asserts DIR to indicate that the PLL is locked. The USB3320 is guaranteed
to start the clock within the time specified in
Host applications the ULPI AutoResume bit should be enabled. This is described in
When using ULPI Output Clock Mode, the edges of the reference clock do not need to be aligned in
any way to the ULPI interface signals; in other words, there is no need to align the phase of the
REFCLK and the CLKOUT.
REFCLK Amplitude
The reference clock is connected to the REFCLK pin as shown in the application diagrams,
Figure 8.2
V
positive edge of the REFCLK.
If a digital reference is not available, the REFCLK pin can be driven by an analog sine wave that is
AC coupled into the REFCLK pin. If using an analog clock, the DC bias should be set at the mid-point
of the VDD18 supply using a bias circuit as shown in
300mV peak to peak. The component values provided in
values should be selected to satisfy system requirements.
The REFCLK amplitude must comply with the signal amplitudes shown in
in
DD18
Table
, but can be driven with a square wave from 0V to as high as 3.6V. The USB3320 uses only the
Link
4.2.
Resonator
and
and Caps
- or -
Crystal
Figure
ULPI Clk In
Clock
8.3. The REFCLK pin is designed to be driven with a square wave from 0V to
Figure 5.4 ULPI Output Clock Mode
0.1uF
C
DATASHEET
LOAD
VDD18
28
Table
CLKOUT
REFCLK
4.2, and it will be accurate to within ±500ppm. For
To REFCLK pin
Figure
XO
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Figure 5.5
~ ~
~ ~
5.5. The amplitude must be greater than
SMSC PHY
Oscillator
From PLL
Internal
are for example only. The actual
Table 4.4
To PLL
and the duty cycle
Section
SMSC USB3320
Figure
Datasheet
6.2.4.4.
8.1,