ISP1508BET STEricsson, ISP1508BET Datasheet
ISP1508BET
Specifications of ISP1508BET
Available stocks
Related parts for ISP1508BET
ISP1508BET Summary of contents
Page 1
IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
Page 2
ISP1508A; ISP1508B ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver Rev. 02 — 13 March 2008 1. General description The ISP1508 is a UTMI+ Low Pin Interface (ULPI) Universal Serial Bus (USB) transceiver that is fully compliant with Universal Serial Bus ...
Page 3
NXP Semiconductors I Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) N Supports external charge pump or external V N Complete control over USB termination resistors N Data line and V N ...
Page 4
... Ordering information Part Type number Marking CHIP_SEL polarity [1] ISP1508AET 508A active HIGH [1] ISP1508BET 508B active LOW [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1508A_ISP1508B_2 Product data sheet ISP1508A; ISP1508B Package Name Description TFBGA36 plastic thin fi ...
Page 5
NXP Semiconductors 5. Block diagram A4 CLOCK C6, B6, A6, A5, A3, A2, 8 A1, B1 DATA [7:0] ULPI E5 DIR INTERFACE D6 STP D5 NXT C3 CHIP_SEL E1 CFG0 B4 CFG1 B3 CFG2 GLOBAL CLOCKS F5 XTAL1 F6 XTAL2 ...
Page 6
NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Pin description [1] [2] Symbol Pin Type DATA1 A1 I/O DATA2 A2 I/O DATA3 A3 I/O CLOCK A4 O DATA4 A5 I/O DATA5 A6 I/O DATA0 ...
Page 7
NXP Semiconductors Table 2. Pin description …continued [1] [2] Symbol Pin Type DM C1 AI/O RREF C2 AI/O CHIP_SEL C3 I TEST_N C4 I DATA7 PSW_N D4 OD NXT D5 O STP ...
Page 8
NXP Semiconductors Table 2. Pin description …continued [1] [2] Symbol Pin Type AI/O BUS XTAL1 F5 AI/O XTAL2 F6 AI/O [1] Symbol names ending with underscore N (for example, NAME_N) indicate active LOW signals. ...
Page 9
NXP Semiconductors 7.3 RREF Resistor reference analog I/O pin RREF pin and GND. This provides an accurate voltage reference that biases internal analog circuitry. Less accurate resistors cannot be used. It will affect the biasing current for ...
Page 10
NXP Semiconductors 7.7 ID For OTG applications, the ID (identification) pin is connected to the ID pin of the micro-AB receptacle. As defined in On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 , the ID pin dictates the initial ...
Page 11
NXP Semiconductors Fig 3. 7.10 REG3V3 and REG1V8 These are output voltage pins from the internal regulator. These supplies are used internally to power digital and analog circuits. For proper operation of the regulator, REG3V3 and REG1V8 must each be ...
Page 12
NXP Semiconductors Table 5. CFG1 When a clock is driven into XTAL1, XTAL2 must be left open crystal is attached, it requires a capacitor on each terminal of the crystal to GND. The recommended crystal ...
Page 13
NXP Semiconductors 7.14 STP ULPI stop input pin. Synchronous to the rising edge of CLOCK. The link must assert STP to signal the end of a USB transmit packet or a register write operation. When DIR is asserted, the link ...
Page 14
NXP Semiconductors 8. Functional description 8.1 ULPI interface controller The ISP1508 provides an 8-pin or 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . This interface must be connected to a USB link. The ...
Page 15
NXP Semiconductors • High-speed disconnect detector • 45 • 1.5 k pull-up resistor on DP • bus terminations on DP and DM For details on controlling resistor settings, see 8.4 Voltage regulator The ISP1508 contains a built-in voltage ...
Page 16
NXP Semiconductors • From DP (2.7 V level) to DATA1 (V 8.7 OTG module This module contains several sub-blocks that provide all the functionality required by the USB OTG specification. Specifically, it provides the following circuits: • The ID detector ...
Page 17
NXP Semiconductors 8.7.3 SRP charge and discharge resistors The ISP1508 provides on-chip resistors for short-term charging and discharging of V These are used by the B-device to request a session, prompting the A-device to restore the V BUS previous session ...
Page 18
NXP Semiconductors Fig 5. 8.11 Power-up, reset and bus idle sequence Figure 6 On power-up, the ISP1508 performs an internal power-on reset and asserts DIR to indicate to the link that the ULPI bus cannot be used. When the internal ...
Page 19
NXP Semiconductors CC(I/O) CHIP_SEL REG1V8 t PWRUP Internal POR XTAL1 CLOCK (output) DATA[7:0] DIR STP NXT applied to the ISP1508 turned on. ULPI interface pins ...
Page 20
NXP Semiconductors The interface protect feature prevents unwanted activity of the ISP1508 whenever the ULPI interface is not correctly driven by the link. For example, when the link powers up more slowly than the ISP1508. The interface protect feature can ...
Page 21
NXP Semiconductors 9. Modes of operation 9.1 Power modes When both V to all the remaining pins, including V range will not damage the ISP1508 chip. When both V ISP1508 will be fully functional as in normal mode. When V ...
Page 22
NXP Semiconductors using pull-up or pull-down resistors to avoid floating input condition. Other pins (see Section detect the CHIP_SEL pin status. 9.2 ULPI modes The ISP1508 ULPI interface can be programmed to operate in five modes. In each mode, the ...
Page 23
NXP Semiconductors Table 9. ULPI signal description Signal name Direction on Signal description the ISP1508 DIR O Direction: Controls the direction of data bus DATA[7:0]. In synchronous mode, the ISP1508 drives DIR to LOW by default, making the data bus ...
Page 24
NXP Semiconductors 9.2.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1508 to 6-pin serial mode. In 6-pin serial mode, the ...
Page 25
NXP Semiconductors Table 12. Signal mapping for 3-pin serial mode Signal Maps to SE0 DATA2 INT DATA3 Reserved DATA[7:4] 9.2.5 Transparent UART mode In transparent UART mode, the ISP1508 functions as a voltage level shifter between the following pins: • ...
Page 26
NXP Semiconductors After the register configuration is complete weak pull-up resistor will be enabled on the DP and DATA0 pins. This is to avoid the possible floating condition on these input pins when UART mode is enabled. 2. ...
Page 27
NXP Semiconductors (1) CLOCK (2) CLOCK DATA[7:0] DIR STP NXT UART mode (1) Clock remains powered when the CLOCK_SUSPENDM register bit is logic 1. (2) Clock is powered down when the CLOCK_SUSPENDM register bit is logic 0 (default). Fig 8. ...
Page 28
NXP Semiconductors 9.3 USB state transitions A Hi-Speed USB peripheral, host or OTG device handles more than one electrical state as defined in Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 . ...
Page 29
NXP Semiconductors Table 14. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR SELECT [1:0] Peripheral 01b high-speed or full-speed suspend Peripheral 01b high-speed or full-speed resume Peripheral Test J or 00b Test K OTG settings OTG ...
Page 30
NXP Semiconductors 10. Protocol description 10.1 ULPI references The ISP1508 provides an 8-pin or 12-pin ULPI interface to communicate with the link highly recommended that users of the ISP1508 read UTMI+ Specification Rev. 1.0 and UTMI+ Low Pin ...
Page 31
NXP Semiconductors The ISP1508 will automatically send an RXCMD whenever there is a change in any of the RXCMD data fields. The link must be able to accept an RXCMD at any time; including single RXCMDs, back-to-back RXCMDs, and RXCMDs ...
Page 32
NXP Semiconductors Table 17. LINESTATE[1:0] encoding for upstream facing ports: peripheral [1] DP_PULLDOWN = 0. Mode XCVRSELECT[1:0] TERMSELECT LINESTATE[1: [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. Table 18. LINESTATE[1:0] encoding for downstream facing ports: ...
Page 33
NXP Semiconductors USE_EXT_VBUS_IND, IND_PASSTHRU Fig 11. RXCMD A_VBUS_VLD indicator source 10.2.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable the corresponding interrupts in the USB Interrupt Enable Rising ...
Page 34
NXP Semiconductors OTG devices: provide a minimum there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD comparator is sufficient. If the OTG A-device provides more than 100 overcurrent ...
Page 35
NXP Semiconductors 10.3 Register read and write operations Figure 12 addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ISP1508 asserts DIR during the operation. When a ...
Page 36
NXP Semiconductors than 7 ms after reset time T up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 ...
Page 37
NXP Semiconductors USB reset T 0 TXCMD (REGW) SE0 DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD SE0 (REGW) DATA [ 7:0 ] DIR ...
Page 38
NXP Semiconductors 10.5 USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . link sends TXCMD CLOCK TXCMD DATA[7:0] DIR STP NXT ...
Page 39
NXP Semiconductors Table 23. Link decision times Packet sequence High-speed link delay Transmit-Transmit (host only) Receive-Transmit (host or peripheral) Receive-Receive 1 (peripheral only) Transmit-Receive 92 (host or peripheral DATA DM CLOCK D ...
Page 40
NXP Semiconductors DP or DATA EOP DM CLOCK DATA [7: DIR STP NXT RX end delay (three to eight clocks) Fig 16. High-speed receive-to-transmit packet timing 10.6 ...
Page 41
NXP Semiconductors CLOCK DATA[7: Fig 17. Preamble sequence 10.7 USB suspend and resume 10.7.1 Full-speed or low-speed host-initiated suspend and resume Figure 18 suspend and sometime later initiates resume signaling to wake-up the downstream peripheral. Note that ...
Page 42
NXP Semiconductors idle DATA [ 7:0 ] DIR STP NXT OPMODE 00b LINE J STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT OPMODE SUSPEND M LINE STATE DP DM Timing is not to scale. Fig 18. Full-speed ...
Page 43
NXP Semiconductors The sequence of events related to a host and a peripheral, both with ISP1508 follows. 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN ...
Page 44
NXP Semiconductors HS idle TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !SQUELCH SQUELCH (00b) (01b) LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM ...
Page 45
NXP Semiconductors 10.7.3 Remote wake-up The ISP1508 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of ...
Page 46
NXP Semiconductors LINESTATE DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 20. Remote ...
Page 47
NXP Semiconductors PHY will not transmit any EOP. The ISP1508 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the ...
Page 48
NXP Semiconductors 10.9.1 OTG comparators The ISP1508 provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 requirements of V and V B_SESS_END V A_SESS_VLD are communicated to the link by RXCMDs as described in comparators ...
Page 49
NXP Semiconductors SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV Fig 22. Example of transmit followed by receive in 6-pin serial mode SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 ...
Page 50
NXP Semiconductors 10.11 Aborting transfers The ISP1508 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4. 10.12 Avoiding contention on the ULPI data bus Because the ULPI data ...
Page 51
NXP Semiconductors 11. Register map Table 24. Register map Field name Size (bit) Vendor ID Low 8 Vendor ID High 8 Product ID Low 8 Product ID High 8 Function Control 8 Interface Control 8 OTG Control 8 USB Interrupt ...
Page 52
NXP Semiconductors 11.1.3 Product ID Low register The bit description of the Product ID Low register is given in Table 27. Product ID Low register (address R = 02h) bit description Legend: * reset value Bit Symbol Access 7 to ...
Page 53
NXP Semiconductors Table 30. Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description OPMODE[1:0] Operation Mode: Selects the required bit-encoding style during transmit. ...
Page 54
NXP Semiconductors Table 32. Interface Control register (address R = 07h to 09h 07h 08h 09h) bit description Bit Symbol Description 7 INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1508 to protect ...
Page 55
NXP Semiconductors Table 33. OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit allocation Bit 7 Symbol USE_EXT_ DRV_ VBUS_IND VBUS_EXT Reset 0 Access R/W/S/C R/W/S/C Table 34. OTG Control ...
Page 56
NXP Semiconductors Table 35. USB Interrupt Enable Rising register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit allocation Bit 7 Symbol reserved Reset 0 Access R/W/S/C R/W/S/C Table 36. USB Interrupt Enable ...
Page 57
NXP Semiconductors 11.7 USB Interrupt Status register This register (see Table 39. USB Interrupt Status register (address R = 13h) bit allocation Bit 7 Symbol reserved Reset X Access R Table 40. USB Interrupt Status register (address R = 13h) ...
Page 58
NXP Semiconductors Table 42. USB Interrupt Latch register (address R = 14h) bit description Bit Symbol ID_GND_L 3 SESS_END_L 2 SESS_VALID_L 1 VBUS_VALID_L 0 HOST_DISCON_L 11.9 Debug register The bit allocation of the Debug register ...
Page 59
NXP Semiconductors For bit allocation, see Table 46. Carkit Control register (address R = 19h to 1Bh 19h 1Ah 1Bh) bit allocation Bit 7 Symbol Reset 0 Access R/W/S/C R/W/S/C Table 47. Carkit Control ...
Page 60
NXP Semiconductors 12. Limiting values Table 50. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I ...
Page 61
NXP Semiconductors 14. Static characteristics Table 52. Static characteristics: supply pins CC(I/O) Typical case refers 3 Symbol Parameter ...
Page 62
NXP Semiconductors Table 53. Static characteristics: digital pins Digital pins: CLOCK, DIR, STP, NXT, DATA[7:0], CHIP_SEL, CFG2, CFG1, TEST_N CC(I/O) Typical case refers to ...
Page 63
NXP Semiconductors Table 56. Static characteristics: analog pins (DP CC(I/O) Typical case refers 3 Symbol Parameter Input ...
Page 64
NXP Semiconductors Table 56. Static characteristics: analog pins (DP CC(I/O) Typical case refers 3 Symbol Parameter Leakage ...
Page 65
NXP Semiconductors Table 58. Static characteristics: ID detection circuit CC(I/O) Typical case refers 3 Symbol Parameter t ID ...
Page 66
NXP Semiconductors 15. Dynamic characteristics Table 62. Dynamic characteristics: reset and power CC(I/O) Symbol Parameter t internal power-on reset pulse W(POR) width t REG1V8 ...
Page 67
NXP Semiconductors Table 65. Dynamic characteristics: digital I/O pins (SDR CC(I/O) Symbol Parameter Conditions t set-up time set-up time with respect to the positive ...
Page 68
NXP Semiconductors Table 67. Dynamic characteristics: analog I/O pins (DP, DM) in USB mode CC(I/O) Symbol Parameter t fall time FF t differential rise ...
Page 69
NXP Semiconductors Table 69. Dynamic characteristics: analog I/O pins (DP, DM) in serial mode CC(I/O) Symbol Parameter Driver timing t driver propagation delay (LOW ...
Page 70
NXP Semiconductors HSR Fig 24. Rise time and fall time 1.8 V logic 0.9 V input PZH t PZL V OH differential ...
Page 71
NXP Semiconductors 16. Application information Table 70. Recommended bill of materials Designator Application R mandatory in all applications RREF R recommended for peripherals S(VBUS) or external 5 V applications C in all applications XTAL C mandatory for peripherals VBUS mandatory ...
Page 72
R S(VBUS BUS USB STANDARD-B RECEPTACLE 4 GND C VBUS 5 SHIELD 6 SHIELD (1) Connect to either GND depending on the clock frequency used. See CC(I/O) Fig 29. ISP1508 in ...
Page 73
V IN FAULT V BUS R pullup SWITCH ON OUT 1 V BUS USB ID MICRO-AB RECEPTACLE 5 GND C VBUS 6 SHIELD IP4359CX4/LF 7 SHIELD 8 SHIELD 9 SHIELD C bypass (1) Connect ...
Page 74
V IN FAULT V BUS R pullup SWITCH ON OUT V 1 BUS USB STANDARD-A RECEPTACLE GND 4 C VBUS SHIELD 5 SHIELD 6 C bypass (1) Connect to either GND depending ...
Page 75
NXP Semiconductors 17. Package outline TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm ball A1 index area 1 ball A1 1 index area ...
Page 76
NXP Semiconductors 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction ...
Page 77
NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
Page 78
NXP Semiconductors Fig 33. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Soldering of through-hole mount packages 19.1 Introduction to soldering through-hole mount ...
Page 79
NXP Semiconductors 19.4 Package related soldering information Table 73. Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL [2] PMFP [1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [2] For ...
Page 80
NXP Semiconductors Table 74. Acronym SE0 SOC SOF SRP SYNC TTL TXCMD TXD UART ULPI USB USB-IF UTMI UTMI+ WLCSP 21. Glossary A-device — An OTG device with an attached micro-A plug. B-device — An OTG device with an attached ...
Page 81
NXP Semiconductors 23. Revision history Table 75. Revision history Document ID Release date ISP1508A_ISP1508B_2 20080313 • Modifications: Changed On-The-Go Supplement to the USB 2.0 Specification from Rev. 1.2 to Rev. 1.3. • Changed JESD22-C101-A to JESD22-C101C • Section 2 ULPI-compliant ...
Page 82
NXP Semiconductors 24. Legal information 24.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
Page 83
NXP Semiconductors 26. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . ...
Page 84
NXP Semiconductors Table 58. Static characteristics: ID detection circuit . . . .64 Table 59. Static characteristics: resistor reference . . . . .64 Table 60. Static characteristics: regulator . . . . . . . . . . . ...
Page 85
NXP Semiconductors 27. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration ...
Page 86
NXP Semiconductors 28. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
Page 87
NXP Semiconductors 11.1.1 Vendor ID Low register . . . . . . . . . . . . . . . . . . 50 11.1.2 Vendor ID High register . . . . . . . . . ...