ISP1508BET STEricsson, ISP1508BET Datasheet - Page 38

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ISP1508BET

Manufacturer Part Number
ISP1508BET
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1508BET

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Table 22.
ISP1508A_ISP1508B_2
Product data sheet
Parameter name
RXCMD delay (J and K)
RXCMD delay (SE0)
TX start delay
TX end delay (packets)
TX end delay (SOF)
RX start delay
RX end delay
Fig 14. Example of using the ISP1508 to transmit and receive USB data
DATA[7:0]
CLOCK
NXT
STP
DIR
PHY pipeline delays
10.5.1.1 ISP1508 pipeline delays
10.5.1.2 Allowed link decision time
10.5.1 USB packet timing
10.5 USB packet transmit and receive
An example of a packet transmit and receive is shown in
packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 .
The ISP1508 delays are shown in
Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.2.6.2 .
The amount of clock cycles allocated to the link to respond to a received packet and
correctly receive back-to-back packets is given in
values given in
packet sequences and timing are shown in
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.2.6.3 .
link sends
TXCMD
TXCMD
High-speed PHY delay
4
4
1 to 2
3 to 4
6 to 9
5 to 6
5 to 6
ISP1508
TXCMD
accepts
Table 23
the next data;
DATA
link sends
ISP1508
accepts
Rev. 02 — 13 March 2008
for correct USB system operation. Examples of high-speed
end of data
link signals
Table
Full-speed PHY delay
4
4 to 6
6 to 10
not applicable
not applicable
not applicable
17 to 18
ULPI bus
22. For detailed description, refer to UTMI+ Low
is idle
Figure 15
ISP1508A; ISP1508B
turnaround
asserts DIR,
turnaround
ISP1508
causing
Table
cycle
and
23. Link designs must follow the
RXCMD
Figure
ULPI HS USB OTG transceiver
(NXT LOW)
Figure
ISP1508
RXCMD
sends
Low-speed PHY delay
4
16 to 18
74 to 75
not applicable
not applicable
not applicable
122 to 123
14. For details on USB
16. For details, refer to
DATA
(NXT HIGH)
USB data
ISP1508
sends
© NXP B.V. 2008. All rights reserved.
turnaround
DIR, causing
turnaround
deasserts
ISP1508
cycle
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