ISP1508BET STEricsson, ISP1508BET Datasheet - Page 53

• Manufacturer Part Number: ISP1508BET
• Manufacturer: STEricsson

Specifications of ISP1508BET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 30.
Table 31.
ISP1508A_ISP1508B_2
Product data sheet
Bit
4 to 3
2
1 to 0
Bit
Symbol
Reset
Access
Symbol
OPMODE[1:0]
TERMSELECT
XCVRSELECT
[1:0]
Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit description
Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation
PROT_DIS
R/W/S/C
11.3 Interface Control register
INTF_
7
0
The Interface Control register enables alternative interfaces. All of these modes are
optional features provided for legacy link cores. Setting more than one of these fields
results in undefined behavior.
IND_PASS
R/W/S/C
Description
Operation Mode: Selects the required bit-encoding style during transmit.
00b — Normal operation
01b — Non-driving
10b — Disable bit-stuffing and NRZI encoding
11b — Do not automatically add SYNC and EOP when transmitting; must be used only for
high-speed packets
Termination Select: Controls the internal 1.5 k full-speed pull-up resistor and 45
high-speed terminations. Control over bus resistors changes, depending on
XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in
Table
Transceiver Select: Selects the required transceiver speed.
00b — Enable the high-speed transceiver
01b — Enable the full-speed transceiver
10b — Enable the low-speed transceiver
11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is
automatically prefixed)
THRU
6
0
14.
R/W/S/C
COMPL
IND_
5
0
Rev. 02 — 13 March 2008
reserved
R/W/S/C
Table 31
4
0
provides the bit allocation of the register.
SUSPENDM
CLOCK_
R/W/S/C
ISP1508A; ISP1508B
3
0
CARKIT_
R/W/S/C
MODE
ULPI HS USB OTG transceiver
2
0
3PIN_FSLS
_SERIAL
R/W/S/C
1
0
© NXP B.V. 2008. All rights reserved.
…continued
6PIN_FSLS
_SERIAL
R/W/S/C
0
0
52 of 86