TZA3044TT/C2 NXP Semiconductors, TZA3044TT/C2 Datasheet - Page 4

• Manufacturer Part Number: TZA3044TT/C2
• Manufacturer: NXP Semiconductors

Specifications of TZA3044TT/C2

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
PINNING
Note
1. Pin type abbreviations: O = Output, I = Input, S = power Supply and A = Analog function.
2002 Jul 19
SYMBOL
SUB
TEST
AGND
DIN
DINQ
V
CF
JAM
STQ
ST
DGND
DOUTQ
DOUT
V
V
RSET
n.c.
CCA
CCD
ref
SDH/SONET STM4/OC12 and 1.25
Gbits/s Gigabit Ethernet postamplifiers
TZA3044B
TZA3044
PIN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
2, 10, 15, 21,
TZA3044BU
TZA3044U
19, 20, 22,
3, 4, 6, 9
5, 31, 32
11, 12
27, 28
1, 14
PAD
26
13
16
17
18
25
23
24
29
30
7
8
TYPE
O
O
O
O
O
S
S
S
A
S
S
A
I
I
I
(1)
substrate pin; must be at the same potential as pin AGND
for test purpose only; to be left open in the application
analog ground; must be at the same potential as pin DGND
differential input; complementary to pin DINQ; DC bias level is set
internally at approximately 2.1 V
differential input; complementary to pin DIN; DC bias level is set
internally at approximately 2.1 V
analog supply voltage; must be at the same potential as pin V
input for connection of capacitor to set time constant of level
detector input filter (optional); the capacitor should be connected
between V
PECL-compatible input (TTL compatible for the TZA3044B);
controls the output buffers pins DOUT and DOUTQ; when a LOW
signal is applied, the outputs will follow the input signal; when a
HIGH signal is applied, the output buffers will latch into LOW and
HIGH states respectively; when not connected, pin JAM is actively
pulled LOW
PECL-compatible status output of the input signal level detector
(TTL compatible for the TZA3044B); when the input signal is below
the user-programmed threshold level, this output is HIGH;
complementary to pin ST
PECL-compatible status output of the input signal level detector
(TTL compatible for the TZA3044B); when the input signal is below
the user-programmed threshold level, this output is LOW;
complementary to pin STQ
digital ground; must be at the same potential as pin AGND
PECL-compatible differential output; forced into a HIGH condition
when pin JAM is HIGH; complementary to pin DOUT
PECL-compatible differential output; forced into a LOW condition
when pin JAM is HIGH; complementary to pin DOUTQ
digital supply voltage; must be at the same potential as V
band gap reference voltage; typical value is 1.2 V; internal series
resistor of 1 k
input signal level detector programming; nominal DC voltage is
V
resistor between V
pin RSET; default value for this resistor is 180 k which
corresponds with approximately 4 mV (p-p) differential input signal
not connected
CCA
4
1.5 V; threshold level is set by connecting an external
CCA
and pin CF
CCA
and pin RSET or by forcing a current into
DESCRIPTION
TZA3044; TZA3044B
Product specification
CCA
CCD