LTC4225CGN-1#TRPBF Linear Technology, LTC4225CGN-1#TRPBF Datasheet - Page 14

• Manufacturer Part Number: LTC4225CGN-1#TRPBF
• Manufacturer: Linear Technology

Specifications of LTC4225CGN-1#TRPBF

• Lead Free Status / RoHS Status: Compliant

LTC4225-1/LTC4225-2
applicaTions inForMaTion
Supply Undervoltage Monitor
The ON pin functions as a turn-on control and an input
supply monitor. A resistive divider connected between
the input supply (IN1, IN2) and GND at the respective
ON pin monitors the supply undervoltage condition. The
undervoltage threshold is set by proper selection of the
resistors and is given by:
where V
An undervoltage fault occurs if the input supply falls below
its undervoltage threshold for longer than 20µs. The FAULT
pin will not be pulled low. If the ON pin voltage falls below
1.155V but remains above 0.6V, the Hot Swap MOSFET is
turned off by a 300µA pull-down from HGATE to ground.
The Hot Swap MOSFET turns back on instantly without
the 100ms debounce cycle when the input supply rises
above its undervoltage threshold.
However, if the ON pin voltage drops below 0.6V, it turns
off the Hot Swap MOSFET and clears the associated fault
latches. The Hot Swap MOSFET turns back on only after a
100ms debounce cycle when the input supply is restored
above its undervoltage threshold. An undervoltage fault on
one supply does not affect the operation of the other sup-
ply. The ideal diode function controlled by the ideal diode
MOSFET is unaffected by undervoltage fault conditions.
14
10V/DIV
20A/DIV
1V/DIV
HGATE
5V/DIV
V
FAULT
I
LOAD
IN(UVTH)
TMR
ON(TH)
Figure 6. Auto-Retry Sequence After a Fault
= 1+

 
is the ON rising threshold (1.235V).
R
BOTTOM
R
TOP
50ms/DIV

 
• V
ON(TH)
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If both IN supplies fall until the internally generated sup-
ply, INTV
MOSFETs are turned off and the fault latches are cleared.
Operation resumes from a fresh start-up cycle when the
input supplies are restored and INTV
threshold.
There is a 10µs glitch filter on the ON pin to reject supply
glitches. By placing a filter capacitor, C
divider at the ON pin, the glitch filter delay is further extended
by the RC time constant to prevent any false fault.
Power Good Monitor
Internal circuitry monitors the MOSFET gate overdrive
between the HGATE and OUT pins. The power good status
for each supply is reported via its respective open-drain
output, PWRGD1 or PWRGD2. They are normally pulled
high by an external pull-up resistor or the internal 10µA
pull-up. The power good output asserts low when the gate
overdrive exceeds 4.2V during the HGATE start-up. Once
asserted low, the power good status is latched and can only
be cleared by pulling the ON pin low, toggling the EN pin
from low to high, or INTV
The power good output continues to pull low while HGATE
is regulating in active current limit, but pulls high when
the circuit breaker times out and pulls the HGATE pin low.
CPO and DGATE Start-Up
The CPO and DGATE pin voltages are initially pulled up to a
diode below the IN pin when first powered up. CPO starts
ramping up 7µs after INTV
level. Another 40µs later, DGATE also starts ramping up
with CPO. The CPO ramp rate is determined by the CPO
pull-up current into the combined CPO and DGATE pin
capacitances. An internal clamp limits the CPO pin voltage
to 12V above the IN pin, while the final DGATE pin voltage
is determined by the gate drive amplifier. An internal 12V
clamp limits the DGATE pin voltage above IN.
CC
, drops below its 2.2V UVLO threshold, all the
CC
CC
entering undervoltage lockout.
clears its undervoltage lockout
CC
F
, with the resistive
exceeds its UVLO
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