LTC4225CGN-1#TRPBF Linear Technology, LTC4225CGN-1#TRPBF Datasheet - Page 15

• Manufacturer Part Number: LTC4225CGN-1#TRPBF
• Manufacturer: Linear Technology

Specifications of LTC4225CGN-1#TRPBF

• Lead Free Status / RoHS Status: Compliant

applicaTions inForMaTion
MOSFET Selection
The LTC4225 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
on-resistance, R
age, BV
The gate drive for the ideal diode MOSFET and Hot Swap
MOSFET is guaranteed to be greater than 5V and 4.8V
respectively when the supply voltages at IN1 and IN2 are
between 2.9V and 7V. When the supply voltages at IN1 and
IN2 are greater than 7V, the gate drive is guaranteed to be
greater than 10V. The gate drive is limited to not more than
14V. This allows the use of logic-level threshold N-channel
MOSFETs and standard N-channel MOSFETs above 7V. An
external Zener diode can be used to clamp the potential
from the MOSFET’s gate to source if the rated breakdown
voltage is less than 14V.
The maximum allowable drain-source voltage, BV
must be higher than the supply voltages as the full sup-
ply voltage can appear across the MOSFET. If an input or
output is connected to ground, the full supply voltage will
appear across the MOSFET. The R
enough to conduct the maximum load current, and also
stay within the MOSFET ’s power rating.
CPO Capacitor Selection
The recommended value of the capacitor, C
CPO and IN pins is approximately 10× the input capaci-
tance, C
takes a correspondingly longer time to charge up by the
internal charge pump. A smaller capacitor suffers more
voltage drop during a fast gate turn-on event as it shares
charge with the MOSFET gate capacitance.
Supply Transient Protection
When the capacitances at the input and output are very
small, rapid changes in current during input or output short-
circuit events can cause transients that exceed the 24V
absolute maximum ratings of the IN and OUT pins. To mini-
mize such spikes, use wider traces or heavier trace plating
to reduce the power trace inductance. Also, bypass locally
DSS
ISS
, of the ideal diode MOSFET. A larger capacitor
, and the threshold voltage.
DS(ON)
, the maximum drain-source volt-
DS(ON)
should be small
CP
, between the
DSS
,
with a 10µF electrolytic and 0.1µF ceramic, or alternatively
clamp the input with a transient voltage suppressor (Z1, Z2).
A 10Ω, 0.1µF snubber damps the response and eliminates
ringing (See Figure 11).
Design Example
As a design example for selecting components, consider
a 12V system with a 7.6A maximum load current for the
two supplies (see Figure 1).
First, select the appropriate value of the current sense
resistors (R
the sense resistor value based on the maximum load
current I
rent I
threshold ∆V
as a ratio of I
backfeeding current to flow through the sense resistor
momentarily, without false tripping the circuit breaker on
the higher supply before the reverse turn-off is activated on
the lower supply. Assuming a load current margin of 1.5×,
Choose a 4mΩ sense resistor with a 1% tolerance.
Next, calculate the R
the desired forward drop at maximum load. Assuming a
forward drop, ∆V
connected back-to-back:
The Si7336ADP offers a good choice with a maximum
R
6mΩ for two MOSFETs in the supply path. The input ca-
pacitance, C
exceeding the 10× recommendation, a 0.1µF capacitor is
selected for C
DS(ON)
I
R
R
TRIP(MIN)
DS(ON,TOTAL)
S
TRIP(MIN)
=
LOAD(MAX)
∆V
of 3mΩ at V
SENSE(CB)(MIN)
ISS
I
LTC4225-1/LTC4225-2
S1
TRIP(MIN)
= 1.5 • I
SENSE(CB)(MIN)
TRIP(MIN)
CP1
, of the Si7336ADP is about 5600pF . Slightly
and the lower limit for the circuit breaker
and R
≤
FWD
and C
, the minimum circuit breaker trip cur-
I
LOAD(MAX)
LOAD(MAX)
/I
∆V
GS
DS(ON)
S2
of 60mV across the two MOSFETs
LOAD(MAX)
CP2
) for the 12V supply. Calculate
FWD
= 10V, thereby giving a total of
=
. A load current margin given
at the CPO pins.
47.5mV
of the MOSFET to achieve
11.4A
=
= 1.5 • 7.6A = 11.4A
60mV
is provided for allowing
7.6A
= 4.16mΩ
= 7.9mΩ
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