MT47H128M16RT-25E:C Micron Technology Inc, MT47H128M16RT-25E:C Datasheet - Page 111

• Manufacturer Part Number: MT47H128M16RT-25E:C
• Description: DRAM Chip DDR2 SDRAM 2G-Bit 128Mx16 1.8V 84-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr
• Series: -r

Specifications of MT47H128M16RT-25E:C

• Package: 84FBGA
• Density: 2 Gb
• Address Bus Width: 17 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Clock Rate: 800 MHz
• Maximum Random Access Time: 0.4 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 2G (128M x 16)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Compliant

Figure 64: Bank Write – Without Auto Precharge
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. E 06/10 EN
Bank select
DQS, DQS#
Command
Address
DQ 6
CK#
CKE
A10
DM
CK
NOP 1
T0
Notes:
Bank x
ACT
RA
RA
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. BL = 4 and AL = 0 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T9.
5. Subsequent rising DQS signals must align to the clock within
6. DI n = data-in for column n; subsequent elements are applied in the programmed order.
7.
8.
t CK
these times.
t
t
DSH is applicable during
DSS is applicable during
t RCD
NOP 1
T2
t CH
t CL
WRITE 2
Bank x
Col n
3
T3
WL ± t DQSS (NOM)
WL = 2
NOP 1
t
111
T4
t
DQSS (MAX) and is referenced from CK T6 or T7.
DQSS (MIN) and is referenced from CK T5 or T6.
t WPRE
NOP 1
T5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DI
n
T5n
t DQSL t DQSH t WPST
t RAS
2Gb: x4, x8, x16 DDR2 SDRAM
NOP 1
5
T6
T6n
Transitioning Data
NOP 1
T7
© 2006 Micron Technology, Inc. All rights reserved.
t
DQSS.
t WR
NOP 1
T8
One bank
All banks
Don’t Care
Bank x 4
T9
PRE
WRITE
t RP