NAND08GW3B2CN6E NUMONYX, NAND08GW3B2CN6E Datasheet - Page 33

• Manufacturer Part Number: NAND08GW3B2CN6E
• Description: 8GBIT SLC NAND FLASH TSOP
• Manufacturer: NUMONYX

Specifications of NAND08GW3B2CN6E

• Cell Type: NAND
• Density: 8Gb
• Access Time (max): 25us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

NAND04G-B2D, NAND08G-BxC
Figure 18. Block erase
RB
I/O
An erase operation consists of the following three steps (refer to
1.
2.
3.
The operation is initiated on the rising edge of Write Enable, W, after the Confirm command
is issued. The P/E/R controller handles block erase and implements the verify process.
During the block erase operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Once the program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completed successfully, the write status bit
SR0 is ‘0’, otherwise it is set to ‘1’.
Block Erase
Setup Code
One bus cycle is required to set up the Block Erase command. Only addresses A18-
A28 are used; all other address inputs are ignored
Three bus cycles are then required to load the address of the block to be erased. Refer
to
One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
controller.
60h
Table 8: Address definition (x8 devices)
Block Address
Inputs
Confirm
Code
D0h
for the block addresses of each device
(Erase Busy time)
tBLBH3
Busy
Figure 18: Block
Read Status Register
70h
Device operations
SR0
erase):
ai07593
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