NAND08GW3B2CN6E NUMONYX, NAND08GW3B2CN6E Datasheet - Page 37

• Manufacturer Part Number: NAND08GW3B2CN6E
• Description: 8GBIT SLC NAND FLASH TSOP
• Manufacturer: NUMONYX

Specifications of NAND08GW3B2CN6E

• Cell Type: NAND
• Density: 8Gb
• Access Time (max): 25us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

NAND04G-B2D, NAND08G-BxC
6.11.2
6.11.3
Note:
6.11.4
6.11.5
Table 14.
1. Only valid for cache operations.
SR4, SR3, SR2,
SR7
SR6
SR5
SR1
SR0
Bit
P/E/R controller and cache ready/busy bit (SR6)
Status register bit SR6 has two different functions depending on the current operation.
During cache operations, SR6 acts as a cache ready/busy bit, which indicates whether the
cache register is ready to accept new data. When SR6 is set to '0', the cache register is
busy, and when SR6 is set to '1', the cache register is ready to accept new data.
During all other operations, SR6 acts as a P/E/R controller bit, which indicates whether the
P/E/R controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R
controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive
(device is ready).
P/E/R controller bit (SR5)
The Program/Erase/Read controller bit indicates whether the P/E/R controller is active or
inactive during cache operations. When the P/E/R controller bit is set to ‘0’, the P/E/R
controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive
(device is ready).
This bit is only valid for cache operations.
Error bit (SR0)
The error bit identifies if any errors have been detected by the P/E/R controller. The error bit
is set to ’1’ when a program or erase operation has failed to write the correct data to the
memory. If the error bit is set to ‘0’ the operation has completed successfully.
SR4, SR3, SR2 and SR1 are reserved
Status register bits
Program/Erase/Read controller
Program/Erase/Read controller
Write protection
Generic error
Reserved
Name
(1)
Logic level
‘don’t care’
‘1’
‘0’
'1'
'0'
'1'
'0'
'1'
'0'
Not protected
Protected
P/E/R controller inactive, device ready
P/E/R controller active, device busy
P/E/R controller inactive, device ready
P/E/R controller active, device busy
Error – operation failed
No error – operation successful
Definition
Device operations
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