ISP1581BD,551 NXP Semiconductors, ISP1581BD,551 Datasheet - Page 37
ISP1581BD,551
Manufacturer Part Number
ISP1581BD,551
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1581BD551.pdf
(80 pages)
Specifications of ISP1581BD,551
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Philips Semiconductors
9397 750 13462
Product data
9.4.5 DMA Strobe Timing register (address: 60H)
Table 36:
This 1-byte register controls the strobe timings for the MDMA mode, when the
DMA_MODE bits in the DMA Configuration register have been set to 03H. The bit
allocation is given in
Bit
7 to 6
5
4
3
2
1
0
DMA Hardware register: bit description
Symbol
ENDIAN[1:0]
EOT_POL
MASTER
ACK_POL
DREQ_POL
WRITE_POL
READ_POL
Rev. 06 — 23 December 2004
Table
Description
These bits determine whether the data bus is swapped between
internal RAM and the DMA bus: This only applies for modes
GDMA (slave) and MDMA (master):
00H — normal data representation
16-bit bus: MSB on DATA[15:8], LSB on DATA[7:0]
01H — swapped data representation
16-bit bus: MSB on DATA[7:0], LSB on DATA[15:8]
02H, 03H — reserved.
Note: while operating with 8 bit data bus, ENDIAN bits should be
always set to 00H.
Selects the polarity of the End Of Transfer input (used in GDMA
slave mode only):
0 — EOT is active LOW
1 — EOT is active HIGH.
Selects the DMA master/slave mode:
0 — GDMA slave mode.
1 — MDMA master mode.
Selects the DMA acknowledgement polarity:
0 — DACK is active LOW
1 — DACK is active HIGH.
Selects the DMA request polarity:
0 — DREQ is active LOW
1 — DREQ is active HIGH.
Selects the DIOW strobe polarity:
0 — DIOW is active LOW
1 — DIOW is active HIGH.
Selects the DIOR strobe polarity:
0 — DIOR is active LOW
1 — DIOR is active HIGH.
37.
Hi-Speed USB peripheral controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1581
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