ISP1581BD,551 NXP Semiconductors, ISP1581BD,551 Datasheet - Page 65
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ISP1581BD,551
Manufacturer Part Number
ISP1581BD,551
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1581BD551.pdf
(80 pages)
Specifications of ISP1581BD,551
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Philips Semiconductors
9397 750 13462
Product data
Fig 26. GDMA slave mode timing (BURST > 01H, MODE = 02H).
DREQ is asserted once per N transfers (N is determined by the BURST value). Example shown here: N = 2.
Data strobe: DACK (read/write).
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
(write) DATA [ 15:0 ]
(read) DATA [ 15:0 ]
DIOR/DIOW
DREQ
DACK
(2)
(1)
(1)
HIGH
Fig 27. EOT timing in Split Bus mode.
Fig 28. EOT timing in Generic Processor mode.
t su1
(1) Programmable polarity: shown as active LOW.
(1) Programmable polarity: shown as active LOW.
Note: EOT should be valid for 36 ns (minimum) when DIOR/DIOW is active.
Note: EOT should be valid for 36 ns (minimum) when RD/WR is active.
t d2
t w1
t su2
Rev. 06 — 23 December 2004
RD/WR
EOT
DREQ
DIOR/DIOW
(1)
t h2
EOT
DREQ
t w2
t h3
(1)
(1)
T cy1
t h1
36 ns (min)
t h1
36 ns (min)
t h1
Hi-Speed USB peripheral controller
t d1
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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ISP1581
MGT505
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