ISP1581BD,551 NXP Semiconductors, ISP1581BD,551 Datasheet - Page 8

• Manufacturer Part Number: ISP1581BD,551
• Manufacturer: NXP Semiconductors

Specifications of ISP1581BD,551

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 13462
Product data
Table 2:
Symbol
READY/
IORDY
DGND
V
CS
(R/W)/RD
DS/WR
INT
ALE/A0
AD0
CC(3.3)
[3]
[1]
Pin description for LQFP64
Pin
22
23
24
25
26
27
28
29
30
Rev. 06 — 23 December 2004
Type
I/O
-
-
I
I
I
O
I
I/O
[2]
Description
Generic processor mode: ready signal (READY; output)
A LOW level signals that ISP1581 is processing a previous
command or data and is not ready for the next command or
data transfer; a HIGH level signals that ISP1581 is ready
for the next microprocessor read or write.
Split Bus mode: DMA ready signal (IORDY; input); used
for accessing ATA/ATAPI peripherals (PIO and UDMA
modes only).
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
digital ground
supply voltage (3.3 V
circuits or it is the tapped out voltage from the internal
regulator; this regulated voltage cannot be used to drive
external devices; see
chip select input; TTL; 5 V tolerant.
input; function is determined by input MODE0 at power-up:
MODE0 = 0 — pin functions as R/W (Motorola style)
MODE0 = 1 — pin functions as RD (8051 style).
input pad; TTL with hysteresis; 5 V tolerant.
input; function is determined by input MODE0 at power-up:
MODE0 = 0 — pin functions as DS (Motorola style)
MODE0 = 1 — pin functions as WR (8051 style).
input pad; TTL with hysteresis; 5 V tolerant.
interrupt output; programmable polarity (active HIGH or
LOW) and signaling (edge or level triggered)
CMOS output; 5 ns slew rate control.
input; function determined by input MODE1 during
power-up:
MODE1 = 0 — pin functions as ALE (address latch
enable); a falling edge latches the address on the
multiplexed address/data bus (AD[7:0])
MODE1 = 1 — pin functions as A0 (address/data selection
on AD[7:0]); a logic 1 detected on the rising edge of the
WR pulse qualifies AD[7:0] as a register address; a logic 0
detected on the rising edge of the WR pulse qualifies
AD[7:0] as a register data; used in Split Bus mode only.
Remark: Connect to DGND in the Generic Processor
mode.
input pad; TTL; 5 V tolerant.
bit 0 of multiplexed address/data.
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
…continued
Hi-Speed USB peripheral controller
Section 10
0.3 V); supplies internal digital
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1581
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