ISP1161A1BD,118 STEricsson, ISP1161A1BD,118 Datasheet - Page 17

• Manufacturer Part Number: ISP1161A1BD,118
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,118

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1161A1_4
Product data sheet
Fig 16. Internal FIFO buffer RAM access cycle.
8.4 FIFO buffer RAM access by PIO mode
write command
(16 bits)
Since the ISP1161A1 internal memory is structured as a FIFO buffer RAM, the FIFO
buffer RAM is mapped to dedicated register fields. Therefore, accessing the internal FIFO
buffer RAM is similar to accessing the internal control registers in multiple data phases.
Figure 16
cycle, the microprocessor first writes the FIFO buffer RAM’s command code to the
command port, and then writes the data words one by one to the data port until half of the
transfer’s byte count is reached. The HcTransferCounter register (22H to read, A2H to
write) is used to specify the byte count of a FIFO buffer RAM’s read cycle or write cycle.
Every access cycle must be in the same access direction. The read cycle procedure is
similar to the write cycle.
For access to the DC FIFO buffer RAM, see
Fig 15. Accessing DC control registers.
WR
RD
CS
D [ 15:0 ]
A1, A0
shows a complete access cycle of the HC internal FIFO buffer RAM. For a write
FIFO buffer RAM access cycle (transfer counter = 2N)
read/write data
#1 (16 bits)
Rev. 04 — 29 January 2009
DC command
write
code
11
read/write data
#2 (16 bits)
DC register data
(lower word)
USB single-chip host and device controller
Section
write
write
read
read
10
13.
read/write data
DC register data
#N (16 bits)
(upper word)
write
write
read
read
10
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
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