ISP1161A1BD,118 STEricsson, ISP1161A1BD,118 Datasheet - Page 20

• Manufacturer Part Number: ISP1161A1BD,118
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,118

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1161A1_4
Product data sheet
8.6.2 HC’s interrupt output pin (INT1)
To program the four configuration modes of the HC’s interrupt output signal (INT1), set
bits InterruptPinTrigger and InterruptOutputPolarity of the HcHardwareConfiguration
register (20H to read, A0H to write). Bit InterruptPinEnable is used as the master enable
setting for pin INT1.
INT1 has many associated interrupt events, as shown as in
The interrupt events of the Hc PInterrupt register (24H to read, A4H to write) changes the
status of pin INT1 when the corresponding bits of the Hc PInterruptEnable register (25H
to read, A5H to write) and pin INT1’s global enable bit (InterruptPinEnable of the
HcHardwareConfiguration register) are all set to enable status.
However, events that come from the HcInterruptStatus register (03H to read, 83H to write)
affect only bit OPR_Reg of the Hc PInterrupt register. They cannot directly change the
status of pin INT1.
Fig 19. Interrupt pin operating modes.
INT
INT
INT
INT
Rev. 04 — 29 January 2009
Mode 0 level triggered, active LOW
Mode 1 level triggered, active HIGH
Mode 2 edge triggered, active LOW
Mode 3 edge triggered, active HIGH
166 ns
166 ns
INT active
INT active
INT active
INT active
USB single-chip host and device controller
clear or disable INT
clear or disable INT
Figure
MGT944
ISP1161A1
20.
© ST-NXP Wireless 2009. All rights reserved.
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