ISP1161A1BD,118 STEricsson, ISP1161A1BD,118 Datasheet - Page 45

• Manufacturer Part Number: ISP1161A1BD,118
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,118

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

10. HC registers
Table 7.
ISP1161A1_4
Product data sheet
Command (Hex)
read
00
01
02
03
04
05
0D
0E
0F
11
12
13
14
15
16
20
21
22
24
25
write
-
81
82
83
84
85
8D
-
-
91
92
93
94
95
96
A0
A1
A2
A4
A5
HC Control register summary
Register
HcRevision
HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcFmInterval
HcFmRemaining
HcFmNumber
HcLSThreshold
HcRhDescriptorA
HcRhDescriptorB
HcRhStatus
HcRhPortStatus[1]
HcRhPortStatus[2]
HcHardwareConfiguration
HcDMAConfiguration
HcTransferCounter
Hc PInterrupt
Hc PInterruptEnable
The HC contains a set of on-chip control registers. These registers can be read or written
by the Host Controller Driver (HCD). The Control and Status register sets, Frame Counter
register sets, and Root Hub register sets are grouped under the category of HC
Operational registers (32 bits). These operational registers are made compatible to
OpenHCI (Host Controller Interface) Operational registers. This allows the OpenHCI HCD
to be easily ported to the ISP1161A1.
Reserved bits may be defined in future releases of this specification. To ensure
interoperability, the HCD must not assume that a reserved field contains logic 0.
Furthermore, the HCD must always preserve the values of the reserved field. When a
R/W register is modified, the HCD must first read the register, modify the bits desired, and
then write the register with the reserved bits still containing the original value.
Alternatively, the HCD can maintain an in-memory copy of previously written values that
can be modified and then written to the HC register. When a ‘write to set’ or ‘clear the
register’ is performed, bits written to reserved fields must be logic 0.
As shown in
32-bit Operational registers are similar to the offsets defined in the OHCI specification with
the addresses being equal to offset divided by 4.
Table
7, the addresses (the commands for accessing registers) of these
Rev. 04 — 29 January 2009
Width Reference
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
16
16
16
16
Section 10.1.1 on page 45
Section 10.1.2 on page 46
Section 10.1.3 on page 47
Section 10.1.4 on page 48
Section 10.1.5 on page 49
Section 10.1.6 on page 50
Section 10.2.1 on page 52
Section 10.2.2 on page 53
Section 10.2.3 on page 53
Section 10.2.4 on page 54
Section 10.3.1 on page 56
Section 10.3.2 on page 57
Section 10.3.3 on page 58
Section 10.3.4 on page 60
Section 10.3.4 on page 60
Section 10.4.1 on page 63
Section 10.4.2 on page 64
Section 10.4.3 on page 66
Section 10.4.4 on page 67
Section 10.4.5 on page 68
USB single-chip host and device controller
Functionality
HC Control and Status registers
HC Frame Counter registers
HC Root Hub registers
HC DMA and Interrupt Control
registers
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
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