MC9S08QD2CSC Freescale, MC9S08QD2CSC Datasheet
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MC9S08QD2CSC
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... MC9S08QD4 MC9S08QD2 S9S08QD4 S9S08QD2 Data Sheet HCS08 Microcontrollers MC9S08QD4 Rev. 6 10/2010 freescale.com ...
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MC9S08QD4 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • 16 MHz HCS08 CPU (central processor unit) • HC08 instruction set with added BGND instruction • Background debugging system • Breakpoint capability to allow single breakpoint setting during in-circuit debugging ...
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MC9S08QD4 Data Sheet Covers: MC9S08QD4 MC9S08QD2 S9S08QD4 S9S08QD2 MC9S08QD4 Rev. 6 10/2010 ...
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... Nov 08 Revised dc injection current Oct 10 Added T This product incorporates SuperFlash Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006-2010. All rights reserved. 6 Description of Changes Errors.” Section 5.6, “Low-Voltage Detect (LVD) (LVW),” to SPMSC2. ...
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... Analog-to-Digital Converter (ADC10V1) ................................ 93 Chapter 9 Internal Clock Source (S08ICSV1)........................................ 121 Chapter 10 Keyboard Interrupt (S08KBIV2) ............................................ 135 Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) ......................... 143 Chapter 12 Development Support ........................................................... 159 Appendix A Electrical Characteristics...................................................... 173 Appendix B Ordering Information and Mechanical Drawings................ 191 Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev ...
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... MC9S08QD4 Series Memory Maps ...............................................................................................31 4.2 Reset and Interrupt Vector Assignments .........................................................................................32 4.3 Register Addresses and Bit Assignments ........................................................................................33 4.4 RAM ................................................................................................................................................36 4.5 Flash ................................................................................................................................................37 4.5.1 Features .............................................................................................................................37 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 External Signal Description Chapter 3 Modes of Operation Chapter 4 MC9S08QD4 Series MCU Data Sheet, Rev. 6 ...
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... System Real-Time Interrupt Status and Control Register (SRTISC) ................................63 5.8.8 System Power Management Status and Control 1 Register (SPMSC1) ...........................64 5.8.9 System Power Management Status and Control 2 Register (SPMSC2) ...........................65 6.1 Port Data and Data Direction ..........................................................................................................67 10 Chapter 5 Chapter 6 Parallel Input/Output Control MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
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... External Signal Description ............................................................................................................98 8.2.1 Analog Power (V 8.2.2 Analog Ground (V 8.2.3 Voltage Reference High (V 8.2.4 Voltage Reference Low (V 8.2.5 Analog Channel Inputs (ADx) ..........................................................................................99 8.3 Register Definition ..........................................................................................................................99 8.3.1 Status and Control Register 1 (ADCSC1) ........................................................................99 Freescale Semiconductor Chapter 7 Chapter 8 ) ....................................................................................................99 DDAD ) ...................................................................................................99 SSAD ) .....................................................................................99 REFH ) ......................................................................................99 REFL MC9S08QD4 Series MCU Data Sheet, Rev ...
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... Operational Modes ..........................................................................................................128 9.4.2 Mode Switching ..............................................................................................................130 9.4.3 Bus Frequency Divider ...................................................................................................130 9.4.4 Low Power Bit Usage .....................................................................................................131 9.4.5 Internal Reference Clock ................................................................................................131 9.4.6 Optional External Reference Clock ................................................................................131 9.4.7 Fixed Frequency Clock ...................................................................................................132 12 Chapter 9 MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
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... Center-Aligned PWM Mode ...........................................................................................156 11.5 TPM Interrupts ..............................................................................................................................157 11.5.1 Clearing Timer Interrupt Flags .......................................................................................157 11.5.2 Timer Overflow Interrupt Description ............................................................................157 11.5.3 Channel Event Interrupt Description ..............................................................................158 11.5.4 PWM End-of-Duty-Cycle Events ...................................................................................158 Freescale Semiconductor Chapter 10 Keyboard Interrupt (S08KBIV2) Chapter 11 MC9S08QD4 Series MCU Data Sheet, Rev ...
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... A.9 ADC Characteristics ......................................................................................................................188 A.10 Flash Specifications .......................................................................................................................189 Ordering Information and Mechanical Drawings B.1 Ordering Information ....................................................................................................................191 B.1.1 Device Numbering Scheme ............................................................................................191 B.2 Mechanical Drawings ....................................................................................................................192 14 Chapter 12 Development Support Appendix A Electrical Characteristics Appendix B MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
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... The MC9S08QD4 and MC9S08QD2 devices are qualified for, and are intended to be used in, consumer and industrial applications. • The S9S08QD4 and S9S08QD2 devices are qualified for, and are intended to be used in, automotive applications. Table 1-1 summarizes the features available in the MCUs. Freescale Semiconductor NOTE MC9S08QD4 Series MCU Data Sheet, Rev ...
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... Automotive Devices S9S08QD4 4 KB 256 B 4-ch, 10-bit 8 MHz 2.7 to 5.5 V One 1-ch; one 2-ch Four I/O; one input-only; one output-only 8-pin NB SOIC no yes MC9S08QD4 Series MCU Data Sheet, Rev. 6 MC9S08QD2 2 KB 128 B Yes yes no S9S08QD2 2 KB 128 B Yes no yes Freescale Semiconductor ...
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... When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 1-1. MC9S08QD4 Series Block Diagram Table 1-2 provides the functional versions of the on-chip modules. Freescale Semiconductor BKGD/MS 4-BIT KEYBOARD INTERRUPT MODULE (KBI) 1-CH 16-BIT TIMER/PWM ...
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... Table 1-2. Versions of On-Chip Modules Module (ADC) (CPU) (ICS) (KBI) (TPM) TCLK1 TPM1 RTI COP FIXED FREQ CLOCK (XCLK) BUSCLK ÷ 2 BDC Appendix A, “Electrical Appendix A, “Electrical MC9S08QD4 Series MCU Data Sheet, Rev. 6 Version TCLK2 TPM2 2 FLASH ADC Characteristics.” Characteristics.” Freescale Semiconductor 3 ...
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... Device Pin Assignment Figure 2-1 shows the pin assignments for the 8-pin packages. PTA5/TPM2CH0I/IRQ/ PTA4/TPM2CH0O/BKGD/MS 2.2 Recommended System Connections Figure 2-2 shows pin connections that are common to almost all MC9S08QD4 series application systems. Freescale Semiconductor PTA0/KBI1P0/TPM1CH0/ADC1P0 RESET 1 8 PTA1/KBI1P1/TPM1CH1/ADC1P1 ...
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... MCU power pins as practical to suppress high-frequency noise. 20 MC9S08QD4 PORT BKGD RESET IRQ NOTE 2 Figure 2-2. Basic System Connections MC9S08QD4 Series MCU Data Sheet, Rev. 6 PTA0/KBI1P0/TPM1CH0/ADC1P0 PTA1/KBI1P1/TPM1CH1/ADC1P1 PTA2/KBI1P2/TCLK1/ADC1P2 PTA3/KBI1P3/TCLK2/ADC1P3 PTA4/TPM2CH0O/BKGD/MS PTA5/TPM2CH0I/IRQ/RESET I/O AND PERIPHERAL INTERFACE TO APPLICATION SYSTEM Freescale Semiconductor ...
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... MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. Freescale Semiconductor Internal Clock Source NOTE ...
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... The pullup device is also disabled if the pin is controlled by an analog function. The KBI module and IRQ function when enabled for rising edge detection causes an enabled internal pull device to be configured as a pulldown. 22 Table 2-1. NOTE MC9S08QD4 Series MCU Data Sheet, Rev. 6 Chapter 6, “Parallel Freescale Semiconductor ...
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... both of these analog modules are enabled both will have access to the pin. 4 See Section 5.8, “Reset, Interrupt, and System Control Registers and Control configuring the IRQ module. Freescale Semiconductor Table 2-1. Pin Sharing Priority Alternative Alternative Function Function 3 TPM1CH0 ADC1P0 ...
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... Chapter 2 External Signal Description 24 MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
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... Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev ...
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... MCU is operated in run mode for the first time. When MC9S08QD4 series devices are shipped from the Freescale Semiconductor factory, the flash program memory is erased by default unless specifically noted program can be executed in run mode until the flash memory is initially programmed ...
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... Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default reset states and must be initialized. Freescale Semiconductor Table 3-1. Stop Mode Behavior RAM ...
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... ENBDM bit is set. After entering background debug mode, all background commands are available. Table 3-2 background debug mode is enabled. 28 Support,” of this data sheet. If ENBDM is set when summarizes the behavior of the MCU in stop when entry into the MC9S08QD4 Series MCU Data Sheet, Rev. 6 Table 3-1. The Freescale Semiconductor ...
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... Parallel Port Registers ADC1 ICS TPM1 & TPM2 Voltage Regulator I/O Pins 1 Requires the asynchronous ADC clock and LVD to be enabled, else in standby. Freescale Semiconductor RAM ICS ADC1 Standby Active Optionally on Table 3-3 summarizes the behavior of the MCU in stop when the Table 3-3 ...
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... Chapter 3 Modes of Operation 30 MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
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... UNIMPLEMENTED 55,216 BYTES 0xEFFF 0xF000 FLASH 4096 BYTES 0xFFFF MC9S08QD4 Figure 4-1. MC9S08QD4 Series Memory Maps Freescale Semiconductor 0x0000 DIRECT PAGE REGISTERS 0x005F 0x0060–0x07F RESERVED — 32 BYTES 0x0080–0x0FF RAM — 128 BYTES 0x0100–0x015F RESERVED — 96 BYTES UNIMPLEMENTED ...
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... Chapter 4 Memory Map and Register Definition 4.2 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor-provided equate file for the MC9S08QD4 series. Address (High/Low) 0xFFC0:FFC1 0xFFCE:FFCF ...
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... ADACT 0x0012 ADCRH 0 0x0013 ADCRL ADR7 0x0014 ADCCVH 0 0x0015 ADCCVL ADCV7 0x0016 ADCCFG ADLPC Freescale Semiconductor can use the more efficient direct addressing mode that requires only Table 4-2. Direct-Page Register Summary PTAD5 PTAD4 0 PTADD5 PTADD4 — — — — — ...
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... ELS0B ELS0A ELS1B ELS1A — — — — — — Freescale Semiconductor Bit 0 — — — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — 0 — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — ...
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... During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the flash memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. Freescale Semiconductor Table 4-3. High-Page Register Summary 6 5 ...
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... MC9S08QD4 Series MCU Data Sheet, Rev Bit 0 — — — — — — ADR3 ADR2 ADR1 ADR0 — — — FTRIM — — — — — — FPDIS — — — SEC01 SEC00 ). RAM Freescale Semiconductor — — — — — ...
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... MC9S08QD4 series usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale Semiconductor-provided equate file). LDHX #RamLast+1 ...
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... FCLK FCLK Table 4-5. Program and Erase Times Cycles of FCLK 9 4 4000 20,000 NOTE MC9S08QD4 Series MCU Data Sheet, Rev The times are shown as a number FCLK = 5 μs. Program and erase times Time if FCLK = 200 kHz 45 μs 20 μ 100 ms Freescale Semiconductor ...
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... Ordinarily, when a program or erase command is issued, an internal charge pump associated with the flash memory must be enabled to supply high voltage to the array. Upon completion of the command, the charge pump is turned off. When a burst Freescale Semiconductor is a flowchart for executing all of the commands except for burst START ...
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... This is because the high voltage to the array must be disabled and then enabled again new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array. 40 MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
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... Writing to a flash address before the internal flash clock frequency has been set by writing to the FCDIV register • Writing to a flash address while FCBEF is not set (A new command cannot be started until the command buffer is empty.) Freescale Semiconductor START FACCERR ? 1 CLEAR ERROR ...
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... FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 A15 A14 42 NVPROT).”) Figure 4-4. The FPS bits are used as the upper bits of the A13 A12 A11 A10 A9 Figure 4-4. Block Protection Mechanism MC9S08QD4 Series MCU Data Sheet, Rev. 6 Section 4.7.4, “Flash Freescale Semiconductor ...
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... BKGD/MS low at the rising edge of reset. A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 Chapter 4 Memory Map and Register Definition ...
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... Table 4-4 for the absolute address assignments for all flash registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 4.7.1 Flash Clock Divider Register (FCDIV) Before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits ...
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... PRDIV8 and DIV for selected bus frequencies. PRDIV8 f Bus (Binary) 8 MHz 0 4 MHz 0 2 MHz 0 1 MHz 0 200 kHz 0 150 kHz 0 Freescale Semiconductor Description 4-2. ÷ (DIV + FCLK Bus ÷ (8 × (DIV + 1 FCLK Bus Table 4-7. Flash Clock Divider Settings ...
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... Table 4-8. FOPT Register Field Descriptions Description Section 4.6, Section 4.6, Table 4-9. Security States SEC01:SEC00 Description 0:0 0:1 1:0 unsecured 1:1 MC9S08QD4 Series MCU Data Sheet, Rev SEC01 “Security.” Table “Security.” 1 secure secure secure Freescale Semiconductor 0 SEC00 4-9. When ...
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... Flash Protect Select Bits — When FPDIS = 0, this 7-bit field determines the ending address of unprotected FPS flash locations at the high address end of the flash. Protected flash locations cannot be erased or programmed. 0 Flash Protection Disable FPDIS 0 Flash block specified by FPS7:FPS1 is block protected (program and erase not allowed flash block is protected. Freescale Semiconductor KEYACC 0 ...
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... After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the flash array is completely erased (all 0xFF FPVIOL FACCERR Figure 4-9. Flash Status Register (FSTAT) Description Section 4.5.5, “Access MC9S08QD4 Series MCU Data Sheet, Rev FBLANK Errors.” FACCERR is cleared by Freescale Semiconductor ...
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... Mass erase (all flash) All other command codes are illegal and generate an access error not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. Freescale Semiconductor Execution,” for a detailed discussion of flash programming 5 4 ...
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... Chapter 4 Memory Map and Register Definition 50 MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
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... Illegal opcode detect (ILOP) • Illegal address detect (ILAD) • Background debug forced reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register. Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 Table 5-2) 51 ...
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... Clock Source COPT 0 ~32 kHz 1 ~32 kHz 0 Bus 1 Bus = 1 ms. See t RTI MC9S08QD4 Series MCU Data Sheet, Rev. 6 Section 5.8.5, “System (SOPT2),” for additional COP Overflow Count cycles (32 ms cycles (256 ms cycles 18 2 cycles in the Section A.8.1, RTI Freescale Semiconductor ...
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... RTI that is used to return from the ISR. When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced first (see Table 5-2). Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control NOTE MC9S08QD4 Series MCU Data Sheet, Rev ...
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... INDEX REGISTER (LOW BYTE PROGRAM COUNTER HIGH 1 5 PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame MC9S08QD4 Series MCU Data Sheet, Rev AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...
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... CCR the CPU will finish the current instruction; stack the PCL, PCH and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control NOTE ...
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... IRQIE IRQ pin LVDIE Low voltage detect — Software interrupt COPE Watchdog timer LVDRE Low-voltage detect RSTPE External pin — Illegal opcode — Illegal address — power-on-reset Freescale Semiconductor — — — — — — — — — — — — ...
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... The RTI can be disabled by writing each bit of RTIS to zeroes, and no interrupts will be generated. See Register (SRTISC),” for detailed information about this register. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control level. Both the POR bit and the LVD bit in SRS are set LVDL LVWH Section 5.8.7, “ ...
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... Refer to the direct-page register summary in assignments for all registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Some control bits in the SOPT1, SOPT2 and SPMSC2 registers are related to modes of operation. ...
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... External Reset Pin — Reset was caused by an active-low level on the external reset pin. PIN 0 Reset not caused by external reset pin. 1 Reset came from external reset pin. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Description Sensitivity,” for more details. ...
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... To enter user mode, PTA4/TPM2CH0O/BKGD/MS must be high immediately after issuing WRITE_BYTE command. To enter BDM, PTA4/TPM2CH0O/BKGD/MS must be low immediately after issuing WRITE_BYTE command. See 60 Description Description A.8.1, “Control Timing,” for more information. MC9S08QD4 Series MCU Data Sheet, Rev BDFR Freescale Semiconductor ...
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... RESET. When clear, the pin functions as one of its input only alternative functions. This pin defaults to its input-only port function following an MCU POR. When RSTPE is set, an internal pullup device is enabled on RESET. 0 PTA5/TPM2CH0I/IRQ/RESET pin functions as PTA5, IRQ or TPM2CH0I. 1 PTA5/TPM2CH0I/IRQ/RESET pin functions as RESET. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control ...
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... Part Identification Number — Each derivative in the HCS08 family has a unique identification number. The ID[11:8] MC9S08QD4 series is hard coded to the value 0x011. See also ID bits Description REV1 REV0 ID11 Description MC9S08QD4 Series MCU Data Sheet, Rev ID10 ID9 ID8 Table 5-9. Freescale Semiconductor ...
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... Real-Time Interrupt Enable — This read-write bit enables real-time interrupts. RTIE 0 Real-time interrupts disabled. 1 Real-time interrupts enabled. 2:0 Real-Time Interrupt Delay Selects — These read/write bits select the period for the RTI. See RTIS Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control ID5 ID4 ...
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... MC9S08QD4 Series MCU Data Sheet, Rev. 6 Using 32 kHz ICS Clock Source 3 Period = t ext Disable RTI × 256 t ext × 1024 t ext × 2048 t ext × 4096 t ext × 8192 t ext × 16384 t ext × 32768 t ext Timing,” for the tolerance of this LVDE BGBE Freescale Semiconductor ...
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... This bit can be written only one time after reset. Additional writes are ignored. 2 LVWF will be set in the case when V Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2) Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Description 5 4 PPDF ...
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... Partial Power Down Control — The write-once PPDC bit controls whether stop2 or stop3 mode is selected. PPDC 0 Stop3 mode enabled. 1 Stop2, partial power down, mode enabled. 66 Description = V ). LVD LVDL = V ). LVD LVDH = V ). LVW LVWL = V ). LVW LVWH MC9S08QD4 Series MCU Data Sheet, Rev LVD ). LVW Freescale Semiconductor ...
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... Reading and writing of parallel I/Os is performed through the port data registers. The direction, either input or output, is controlled through the port data direction registers. The parallel I/O port function for an individual pin is illustrated in the block diagram shown in Freescale Semiconductor Description,” for more information about pin NOTE Figure MC9S08QD4 Series MCU Data Sheet, Rev ...
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... Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An explanation of pin behavior for the various stop modes follows: 68 PTxDDn D Q PTxDn Figure 6-1. Parallel I/O Block Diagram MC9S08QD4 Series MCU Data Sheet, Rev. 6 Output Enable Output Data Input Data Synchronizer Freescale Semiconductor ...
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... This section provides information about the registers associated with the parallel I/O ports. Refer to tables in Chapter 4, “Memory Map and Register for all parallel I/O. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. ...
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... The pins associated with port A are controlled by the registers in this section. These registers control the pin pullup, slew rate and drive strength of the Port A pins independent of the parallel I/O register. 70 Table 6-1. PTAD Register Field Descriptions Description PTADD5 PTADD4 PTADD3 0 0 Description MC9S08QD4 Series MCU Data Sheet, Rev PTADD2 PTADD1 Freescale Semiconductor 0 PTADD0 0 ...
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... Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control PTASE[5:0] is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n. Freescale Semiconductor ...
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... PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port A bit n. 1 High output drive strength selected for port A bit PTADS5 PTADS4 PTADS3 Description MC9S08QD4 Series MCU Data Sheet, Rev PTADS2 PTADS1 PTADS0 Freescale Semiconductor ...
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... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several ...
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... For compatibility with the earlier M68HC05 Family forced to 0x00 during reset. Reset has no effect on the contents ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
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... Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code bits in general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. ...
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... No carry out of bit 7 1 Carry out of bit CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Description MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
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... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 Chapter 7 Central Processor Unit (S08CPUV2) ...
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... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 78 MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
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... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the Freescale Semiconductor Resets, Interrupts, and System Configuration MC9S08QD4 Series MCU Data Sheet, Rev. 6 ...
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... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation 80 chapter for more details. MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
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... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 Chapter 7 Central Processor Unit (S08CPUV2) ...
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... rpp prpp prpp 0 – – rpp 3 F4 rfp pprpp 4 ff prpp rfwpp – – rfwpp 4 78 rfwp 6 ff prfwpp rfwpp – – rfwpp 4 77 rfwp 6 ff prfwpp 3 – – – – – – ppp Freescale Semiconductor – – – ...
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... BLT rel BMC rel Branch if Interrupt Mask Clear ( BMI rel Branch if Minus ( BMS rel Branch if Interrupt Mask Set ( BNE rel Branch if Not Equal ( BPL rel Branch if Plus ( Freescale Semiconductor Object Code DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL REL ...
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... AD rr ssppp rpppp 4 pppp pppp – – – – – – rpppp rfppp prpppp 1 – – – – – – – 0 – – – rfwpp – – – rfwpp 4 7F rfwp 6 ff prfwpp Freescale Semiconductor – – – – – – ...
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... DIV A ← (H:A)÷(X); H ← Remainder EOR #opr8i Exclusive OR Memory with Accumulator A ← (A ⊕ M) EOR opr8a EOR opr16a EOR oprx16,X EOR oprx8,X EOR ,X EOR oprx16,SP EOR oprx8,SP Freescale Semiconductor Object Code IMM DIR EXT IX2 IX1 IX SP2 9E D1 SP1 ← ...
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... rpp prpp prpp 0 – – rpp 3 FE rfp pprpp 4 ff prpp rfwpp – – rfwpp 4 78 rfwp 6 ff prfwpp rfwpp – – rfwpp 4 74 rfwp 6 ff prfwpp Freescale Semiconductor – – – – ...
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... C ROL oprx8,X b7 ROL ,X ROL oprx8,SP ROR opr8a Rotate Right through Carry RORA RORX ROR oprx8,X b7 ROR ,X ROR oprx8,SP Freescale Semiconductor Object Code DIR/DIR DIR/IX+ source IMM/DIR IX+/DIR INH M ← – (M) = $00 – (M) DIR INH X ← – (X) = $00 – (X) INH M ← – (M) = $00 – (M) IX1 M ← ...
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... B7 dd wpp pwpp pwpp 0 – – wpp ppwpp 4 ff pwpp wwpp 0 – – pwwpp 5 ff pwwpp 2 – – 0 – – – 8E fp... wpp pwpp pwpp 0 – – wpp ppwpp 4 ff pwpp Freescale Semiconductor – – – ...
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... TST opr8a Test for Negative or Zero TSTA TSTX TST oprx8,X TST ,X TST oprx8,SP Transfer SP to Index Reg. TSX H:X ← (SP) + $0001 Transfer X (Index Reg. Low) to Accumulator TXA A ← (X) Freescale Semiconductor Object Code IMM DIR EXT IX2 IX1 IX SP2 9E D0 SP1 9E E0 INH ...
Page 90
... Read vector from $FFxx (high byte first) v Write 8-bit operand w CCR Effects: Set or cleared – Not affected U Undefined MC9S08QD4 Series MCU Data Sheet, Rev. 6 Cyc-by-Cyc Affect Details on CCR – – – – – – – – 0 – – – 8F fp... Freescale Semiconductor ...
Page 91
... IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Freescale Semiconductor Table 7-3. Opcode Map (Sheet Read-Modify-Write Control NEGX NEG NEG RTI 1 INH ...
Page 92
... IX 4 IX2 3 IX1 4 SP2 3 9EDF 5 9EEF STX 4 SP2 3 Prebyte (9E) and Opcode in 9E60 6 HCS08 Cycles Hexadecimal NEG Instruction Mnemonic Addressing Mode Number of Bytes 3 SP1 Freescale Semiconductor 4 SUB SP1 4 CMP SP1 4 SBC SP1 4 9EF3 6 CPX CPHX SP1 3 SP1 4 AND SP1 4 BIT SP1 4 LDA ...
Page 93
... The ADC module design supports separate analog inputs (AD0–AD27). Only four (ADC1P0–ADC1P3) of the possible inputs are implemented on the MC9S08QD4 series MCU. These inputs are selected by the ADCH bits. Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev ...
Page 94
... V DD – 0.7 V. The internal gates connected to this pin are pulled MC9S08QD4 Series MCU Data Sheet, Rev. 6 IRQ 4 TPM2CH0 PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS TCLK2 PTA3/KBI1P3/TCLK2/ADC1P3 PTA2/KBI1P2/TCLK1/ADC1P2 TPM1CH0 PTA1/KBI1P1/TPM1CH1/ADC1P1 TPM1CH1 PTA0/KBI1P0/TPM1CH0/ADC1P0 TCLK1 4 . The voltage measured on this pin when DD Freescale Semiconductor . DD ...
Page 95
... The period of the RTI is determined by the input clock frequency and the RTIS bits. The RTI counter is a free running counter that generates an overflow at the RTI rate determined by the RTIS bits. When the ADC hardware trigger is enabled, a conversion is initiated upon a RTI counter overflow. Freescale Semiconductor Table 8-1. ADC Channel Assignment Pin Control ...
Page 96
... TEMP 12°C, using Equation 8-1. ± 4.5°C. ± Equation 8-1 as detailed above and then determine if the MC9S08QD4 Series MCU Data Sheet, Rev. 6 Appendix A.5, “DC V TEMP = 3.0V, DD Eqn. 8-1 2.5°C. Once calibration has ± Freescale Semiconductor ...
Page 97
... Asynchronous clock source for lower noise operation. • Selectable asynchronous hardware conversion trigger. • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value. 8.1.3 Block Diagram Figure 8-2 provides a block diagram of the ADC module Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 Analog-to-Digital Converter (S08ADC10V1) 97 ...
Page 98
... Function AD27–AD0 Analog Channel inputs V High reference voltage REFH V Low reference voltage REFL V Analog power supply DDAD V Analog ground SSAD MC9S08QD4 Series MCU Data Sheet, Rev. 6 Async Clock Gen ADACK Bus Clock ÷2 ALTCLK AIEN 1 Interrupt COCO 2 3 Freescale Semiconductor ...
Page 99
... Status and Control Register 1 (ADCSC1) This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). Freescale Semiconductor ) DDAD as its power connection. In some packages, V ...
Page 100
... Figure 8-4. Input Channel Select Input Select AD0 AD1 AD2 AD3 AD4 AD5 AD6 MC9S08QD4 Series MCU Data Sheet, Rev ADCH ADCH Input Select 10000 AD16 10001 AD17 10010 AD18 10011 AD19 10100 AD20 10101 AD21 10110 AD22 Freescale Semiconductor ...
Page 101
... Two types of trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input. 0 Software trigger selected 1 Hardware trigger selected Freescale Semiconductor Input Select AD7 AD8 AD9 ...
Page 102
... In 8-bit mode, there is no interlocking with ADCRH. In the case that the MODE bits are changed, any data in ADCRL becomes invalid. 102 Description MC9S08QD4 Series MCU Data Sheet, Rev ADR9 ADR8 Freescale Semiconductor ...
Page 103
... Bits ADCV7:ADCV0 are compared to the lower 8 bits of the result following a conversion in either 10-bit or 8-bit mode ADCV7 ADCV6 W Reset Figure 8-9. Compare Value Low Register(ADCCVL) 8.3.7 Configuration Register (ADCCFG) ADCCFG is used to select the mode of operation, clock source, clock divide, and configure for low power or long sample time. Freescale Semiconductor ADR5 ADR4 ADR3 ...
Page 104
... Divide Ratio Table 8-7. Conversion Modes Mode Description 8-bit conversion (N=8) Reserved 10-bit conversion (N=10) Reserved MC9S08QD4 Series MCU Data Sheet, Rev MODE ADICLK Table Clock Rate Input clock Input clock ÷ 2 Input clock ÷ 4 Input clock ÷ 8 Freescale Semiconductor 8-7. ...
Page 105
... ADC Pin Control 2 — ADPC2 is used to control the pin associated with channel AD2. ADPC2 0 AD2 pin I/O control enabled 1 AD2 pin I/O control disabled Freescale Semiconductor Table 8-8. Input Clock Select Selected Clock Source Bus clock Bus clock divided by 2 Alternate clock (ALTCLK) ...
Page 106
... ADC Pin Control 10 — ADPC10 is used to control the pin associated with channel AD10. ADPC10 0 AD10 pin I/O control enabled 1 AD10 pin I/O control disabled 106 Description ADPC13 ADPC12 ADPC11 Description MC9S08QD4 Series MCU Data Sheet, Rev ADPC10 ADPC9 ADPC8 Freescale Semiconductor ...
Page 107
... ADPC19 0 AD19 pin I/O control enabled 1 AD19 pin I/O control disabled 2 ADC Pin Control 18 — ADPC18 is used to control the pin associated with channel AD18. ADPC18 0 AD18 pin I/O control enabled 1 AD18 pin I/O control disabled Freescale Semiconductor Description ADPC21 ADPC20 ADPC19 ...
Page 108
... Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the available clocks are too slow, the ADC will not perform according to specifications. If the available clocks 108 Description MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 109
... In software triggered operation, continuous conversions begin after ADCSC1 is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 Analog-to-Digital Converter (S08ADC10V1) ...
Page 110
... ADLSMP is used to select between short and long sample times.When sampling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digital value of the analog signal. The 110 MC9S08QD4 Series MCU Data Sheet, Rev After f ADCK Freescale Semiconductor ...
Page 111
... MHz, then the conversion time for a single conversion is: Conversion time = Number of bus cycles = 3.5 μ MHz = 28 cycles The ADCK frequency must be between f maximum to meet ADC specifications. Freescale Semiconductor frequency, precise sample time for continuous conversions ADCK ADICLK ADLSMP ...
Page 112
... If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a STOP instruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode.After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. 112 NOTE MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 113
... Update the configuration register (ADCCFG) to select the input clock source and the divide ratio used to generate the internal clock, ADCK. This register is also used for selecting sample time and low-power configuration. Freescale Semiconductor NOTE Conversions,”) is cleared when entering stop3 Table ...
Page 114
... Software trigger selected Compare function disabled Not used in this example Unimplemented or reserved, always reads zero Reserved for Freescale’s internal use; always write zero Read-only flag which is set when a conversion completes Conversion complete interrupt enabled One conversion only (continuous conversions disabled) MC9S08QD4 Series MCU Data Sheet, Rev ...
Page 115
... When available on a separate pin, both V as their corresponding MCU digital supply (V noise immunity and bypass capacitors placed as near as possible to the package. Freescale Semiconductor RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ...
Page 116
... MC9S08QD4 Series MCU Data Sheet, Rev some devices. The low DDAD on some devices may be DDAD spec and the V potential (V DDAD must be connected to the same REFL . Setting the pin control register bits for and the input is equal to or REFL , the converter circuit converts it REFL Freescale Semiconductor REFH ...
Page 117
... I/O activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: Place a 0.01 μF capacitor (C • improve noise issues but will affect sample rate based on the external analog source resistance). Freescale Semiconductor lower than REFH REFL ...
Page 118
... Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the 118 LSB REFH REFL ). Note, if the last conversion is $3FE, then the LSB MC9S08QD4 Series MCU Data Sheet, Rev one-time error. LSB Eqn. 8-2 . LSB ). Note, if the first LSB LSB ) is used. LSB Freescale Semiconductor ) is ...
Page 119
... Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Missing codes are those values which are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes. Freescale Semiconductor and will increase with noise. This error may be LSB Errors,” ...
Page 120
... Analog-to-Digital Converter (S08ADC10V1) 120 MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 121
... ICSOUT is two times the bus frequency. Figure 9-1 Shows the MC9S08QD4 series with the ICS module highlighted. 9.1.1 ICS Configuration Information Bit-1 and bit-2 of ICS control register 1 (ICSC1) always read as 1. Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 121 ...
Page 122
... V DD – 0.7 V. The internal gates connected to this pin are pulled MC9S08QD4 Series MCU Data Sheet, Rev. 6 IRQ 4 TPM2CH0 PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS TCLK2 PTA3/KBI1P3/TCLK2/ADC1P3 PTA2/KBI1P2/TCLK1/ADC1P2 TPM1CH0 PTA1/KBI1P1/TPM1CH1/ADC1P1 TPM1CH1 PTA0/KBI1P0/TPM1CH0/ADC1P0 TCLK1 4 . The voltage measured on this pin when DD Freescale Semiconductor . DD ...
Page 123
... FLL. FLL Bypassed Interna 9.1.3.4 In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock derived from the internal reference clock. The BDC clock is not available. Freescale Semiconductor l (FEI) (FEE) l (FBI) l Low Power (FBILP) MC9S08QD4 Series MCU Data Sheet, Rev ...
Page 124
... Low Power (FBELP) Optional EREFS EREFSTEN Block ERCLKEN IRCLKEN IREFSTEN CLKS Internal LP Reference Clock DCOOUT 9 DCO TRIM 9 n RDIV_CLK Filter FLL Internal Clock Source Block MC9S08QD4 Series MCU Data Sheet, Rev. 6 ICSERCLK ICSIRCLK BDIV ICSOUT n=0-3 ICSLCLK / 2 ICSFFCLK Freescale Semiconductor ...
Page 125
... Internal Reference Stop Enable — The IREFSTEN bit controls whether or not the internal reference clock IREFSTEN remains enabled when the ICS enters stop mode. 1 Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before entering stop 0 Internal reference clock is disabled in stop Freescale Semiconductor 5 4 RDIV 0 0 Figure 9-3 ...
Page 126
... External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode before entering stop 0 External reference clock is disabled in stop 126 5 4 RANGE HGO Figure 9-4. ICS Control Register 2 (ICSC2) Description MC9S08QD4 Series MCU Data Sheet, Rev EREFS ERCLKEN EREFSTEN Freescale Semiconductor 0 0 ...
Page 127
... This bit is cleared only when either ERCLKEN or EREFS are cleared. 0 ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency. Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount possible. Freescale Semiconductor TRIM ...
Page 128
... MC9S08QD4 Series MCU Data Sheet, Rev. 6 IREFS=1 CLKS=01 BDM Enabled or LP=0 FLL Bypassed FLL Bypassed Internal Low Internal (FBI) Power(FBILP) IREFS=1 CLKS=01 BDM Disabled and LP=1 Returns to state that was active before MCU entered stop, unless reset occurs while in stop. Freescale Semiconductor ...
Page 129
... In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock. The FLL clock is controlled by the external reference clock, and the FLL loop will lock the FLL frequency to 512 Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 Internal Clock Source (S08ICSV1) ...
Page 130
... If the newly selected clock is not available, the previous clock will remain selected. 9.4.3 Bus Frequency Divider The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur immediately. 130 MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 131
... Overview chapter). If EREFSTEN is set and the ERCLKEN bit is written to 1, the external reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. Freescale Semiconductor chapter). MC9S08QD4 Series MCU Data Sheet, Rev. 6 Internal Clock Source (S08ICSV1) Device ...
Page 132
... IRST reference is stable, the FLL will acquire lock in t Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale recommends using FLASH location 0xFFAE for storing the fine trim bit, FTRIM in the ICSSC register, and 0xFFAF for storing the 8-bit trim value for the ICSTRM register. The MCU will not automatically copy the values in these FLASH locations to the respective registers ...
Page 133
... The CLKST bits in the ICSSC register can be monitored to determine when the mode switch has completed. The CLKST bits will not change when switching from FEE to FEI. If FEI was selected, the bus clock will be stable in t Freescale Semiconductor milliseconds. The CLKST bits will not change when Acquire NOTE milliseconds ...
Page 134
... Internal Clock Source (S08ICSV1) 134 MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 135
... Only four (KBI1P0–KBI1P3) of the possible interrupts are implemented on the MC9S08QD4 series MCU. These inputs are selected by the KBIPE bits. Figure 10-1 Shows the MC9S08QD4 series with the KBI module and pins highlighted. Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 135 ...
Page 136
... ANALOG-TO-DIGITAL CONVERTER (ADC) and must not be driven above V DD – 0.7 V. The internal gates connected to this pin are pulled MC9S08QD4 Series MCU Data Sheet, Rev. 6 IRQ PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS PTA3/KBI1P3/TCLK2/ADC1P3 PTA2/KBI1P2/TCLK1/ADC1P2 PTA1/KBI1P1/TPM1CH1/ADC1P1 PTA0/KBI1P0/TPM1CH0/ADC1P0 . The voltage measured on this pin when DD DD Freescale Semiconductor . ...
Page 137
... KBI in Active Background Mode When the microcontroller is in active background mode, the KBI will continue to operate normally. 10.1.3 Block Diagram The block diagram for the keyboard interrupt module is shown Freescale Semiconductor Figure MC9S08QD4 Series MCU Data Sheet, Rev. 6 Keyboard Interrupts (S08KBIV2) Modes of Operation 10-2 ...
Page 138
... Figure 10-2. KBI Block Diagram Table 10-1. Table 10-1. Signal Properties Function Keyboard interrupt pins Memory chapter for the absolute address assignments for MC9S08QD4 Series MCU Data Sheet, Rev. 6 BUSCLK KBACK RESET KBF SYNCHRONIZER STOP BYPASS STOP KBI INTERRU PT KBIE I/O I Freescale Semiconductor ...
Page 139
... Keyboard Pin Enables — Each of the KBIPEn bits enable the corresponding keyboard interrupt pin. KBIPEn 0 Pin not enabled as keyboard interrupt. 1 Pin enabled as keyboard interrupt. 10.3.3 KBI Edge Select Register (KBIES) KBIES contains the edge select control bits. Freescale Semiconductor KBF 0 ...
Page 140
... A valid edge or level on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing KBACK in 140 KBEDG5 KBEDG4 KBEDG3 Figure 10-5. KBI Edge Select Register Description MC9S08QD4 Series MCU Data Sheet, Rev KBEDG2 KBEDG1 KBEDG0 Freescale Semiconductor ...
Page 141
... If using internal pullup/pulldown device, configure the associated pullup enable bits in PTxPE. 4. Enable the KBI pins by setting the appropriate KBIPEn bits in KBIPE. 5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts. Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 Keyboard Interrupts (S08KBIV2) 141 ...
Page 142
... Keyboard Interrupts (S08KBIV2) 142 MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 143
... When TPM2 is disabled, PTA4 and PTA5 function as standard port pins. 11.1.2 TCLK1 and TCLK2 Configuration Information The TCLK1 and TCLK2 are the external clock source inputs for TPM1 and TPM2 respectively. Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 143 ...
Page 144
... ANALOG-TO-DIGITAL CONVERTER (ADC) and must not be driven above V DD – 0.7 V. The internal gates connected to this pin are pulled MC9S08QD4 Series MCU Data Sheet, Rev. 6 IRQ PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS PTA3/KBI1P3/TCLK2/ADC1P3 PTA2/KBI1P2/TCLK1/ADC1P2 PTA1/KBI1P1/TPM1CH1/ADC1P1 PTA0/KBI1P0/TPM1CH0/ADC1P0 . The voltage measured on this pin when DD DD Freescale Semiconductor . ...
Page 145
... Set, clear, or toggle output compare action — Selectable polarity on PWM outputs 11.1.4 Block Diagram Figure 11-2 shows the structure of a TPM. Some MCUs include more than one TPM, with various numbers of channels. Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 Timer/Pulse-Width Modulator (S08TPMV2) 145 ...
Page 146
... Figure 11-2. TPM Block Diagram MC9S08QD4 Series MCU Data Sheet, Rev. 6 PRESCALE AND SELECT DIVIDE 16, 32, 64, or 128 PS2 PS1 PS0 TOF INTERRUPT LOGIC TOIE PORT TPMxCH0 LOGIC INTERRUPT LOGIC TPMxCH1 PORT LOGIC INTERRUPT LOGIC TPMxCHn PORT LOGIC INTERRUPT LOGIC Freescale Semiconductor ...
Page 147
... A 16-bit channel value register (TPMxCnVH:TPMxCnVL) Refer to the direct-page register summary in the assignments for all TPM registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor Pins and Connections Memory chapter of this data sheet for the absolute address MC9S08QD4 Series MCU Data Sheet, Rev ...
Page 148
... Timer/Pulse-Width Modulator (S08TPMV2) Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.1 Timer Status and Control Register (TPMxSC) TPMxSC contains the overflow status flag and control bits that are used to configure the interrupt enable, TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this timer module ...
Page 149
... Bit Reset 0 0 Figure 11-4. Timer Counter Register High (TPMxCNTH) Freescale Semiconductor Table 11-2. TPM Clock Source Selection TPM Clock Source to Prescaler Input No clock selected (TPMx disabled) Bus rate clock (BUSCLK) Fixed system clock (XCLK) External source (TPMxCLK) Table 11-3. Prescale Divisor Selection ...
Page 150
... An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. 150 Any write to TPMxCNTL clears the 16-bit counter MC9S08QD4 Series MCU Data Sheet, Rev Bit Bit Bit Freescale Semiconductor ...
Page 151
... Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer channel functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general-purpose I/O pin when the associated timer channel is set software timer that does not require the use of a pin. Freescale Semiconductor ...
Page 152
... Clear output on compare 11 Set output on compare 10 Edge-aligned High-true pulses (clear output on compare) PWM X1 Low-true pulses (set output on compare) 10 Center-aligned High-true pulses (clear output on compare-up) PWM X1 Low-true pulses (set output on compare-up MC9S08QD4 Series MCU Data Sheet, Rev. 6 Configuration Bit Bit Freescale Semiconductor ...
Page 153
... Otherwise, the counter operates as a simple up-counter up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL. Freescale Semiconductor (TPMxSC)” MC9S08QD4 Series MCU Data Sheet, Rev. 6 ...
Page 154
... When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. 154 MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 155
... TPMxCnVH or TPMxCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the value in the TPMxCNTH:TPMxCNTL counter is 0x0000. (The new duty cycle does not take effect until the next full period.) Freescale Semiconductor OVERFLOW PERIOD PULSE ...
Page 156
... TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. Values are 156 period = 2 x (TPMxMODH:TPMxMODL); for TPMxMODH:TPMxMODL = 0x0001–0x7FFF COUNT = 0 OUTPUT OUTPUT COMPARE COMPARE (COUNT UP) (COUNT DOWN) PULSE WIDTH 2 x PERIOD 2 x MC9S08QD4 Series MCU Data Sheet, Rev. 6 Eqn. 11-1 Eqn. 11-2 COUNT = TPMxMODH:TPMx Freescale Semiconductor ...
Page 157
... This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) Freescale Semiconductor chapter for absolute interrupt vector addresses, priority, and local MC9S08QD4 Series MCU Data Sheet, Rev ...
Page 158
... The flag is cleared by the 2-step sequence described in 158 Flags.” Section 11.5.1, “Clearing Timer Interrupt MC9S08QD4 Series MCU Data Sheet, Rev. 6 Flags.” Freescale Semiconductor Flags.” ...
Page 159
... MCU will always reset into normal operating mode. 12.1.2 Module Configuration The alternative BDC clock source for MC9S08QD4 series is the ICGCLK. See Source (S08ICSV1),” for more information about ICGCLK and how to select clock sources. Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 Chapter 9, “Internal Clock 159 ...
Page 160
... However, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. 160 MC9S08QD4 Series MCU Data Sheet, Rev. 6 can be used to allow the pod to use DD Freescale Semiconductor ...
Page 161
... BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress Freescale Semiconductor 2 GND ...
Page 162
... MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The host must sample the bit level about 10 cycles after it started the bit time. 162 10 CYCLES TARGET SENSES BIT LEVEL MC9S08QD4 Series MCU Data Sheet, Rev. 6 EARLIEST START OF NEXT BIT Freescale Semiconductor ...
Page 163
... HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time. Freescale Semiconductor HIGH-IMPEDANCE R-C RISE ...
Page 164
... HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used in Table 12-1 164 HIGH-IMPEDANCE 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN to describe the coding structure of the BDC commands. MC9S08QD4 Series MCU Data Sheet, Rev. 6 SPEEDUP PULSE EARLIEST START OF NEXT BIT Freescale Semiconductor ...
Page 165
... BDCSCR in the host-to-target direction (CONTROL) RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) WBKP = 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register) Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 Development Support 165 ...
Page 166
... MC9S08QD4 Series MCU Data Sheet, Rev. 6 Description Request a timed reference pulse to determine target BDC communication speed Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. Enter active background mode if enabled (ignore if ENBDM bit equals 0) ...
Page 167
... The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS = 1) or tagged (FTS = 0) type breakpoints. 12.3 Register Definition This section contains the descriptions of the BDC registers and control bits. Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 6 Development Support 167 ...
Page 168
... Development Support This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 12.3.1 BDC Registers and Control Bits The BDC has two registers: • The BDC status and control register (BDCSCR 8-bit register containing control and status bits for the background debug controller. • ...
Page 169
... Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC clock CLKSW source. 0 Alternate BDC clock source 1 MCU bus clock Freescale Semiconductor BKPTEN FTS CLKSW 0 ...
Page 170
... This register contains a single write-only control bit. A serial background mode command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00. 170 Description Breakpoint.” MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 171
... Table 12-3. SBDFR Register Field Description Field 0 Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. Freescale Semiconductor ...
Page 172
... Development Support 172 MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
Page 173
... This will be the greatest risk when the MCU is not consuming power. Examples are system clock is present the clock rate is very low (which would reduce overall power consumption). Freescale Semiconductor Table A-1 may affect device reliability or cause Table A-1. Absolute Maximum Ratings ...
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... Using this value of K, the values iteratively for any value of T MC9S08QD4 Series MCU Data Sheet, Rev will be very SS DD Value Unit ° –40 to 125 °C 135 °C/W 113 150 °C and T can be obtained Freescale Semiconductor Eqn. A-1 and Eqn. A-2 Eqn. A-3 ...
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... Charge device model (CDM) Latch-up current Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. A.5 DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Freescale Semiconductor Description Symbol R1 C — — ...
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... V — DD 0.3 × V — DD 0.06 × V — DD — 0.025 1.0 Freescale Semiconductor Unit μA ...
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... Measurement condition for pull resistors All functional non-supply pins are internally clamped Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Freescale Semiconductor Symbol | ...
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... Typical Low-side Driver (LDS) Characteristics 5.0 V, PORTA DD 2 0.4 0.8 1.2 1 5.0V Typical Low-side Driver (LDS) Characteristics 3.0 V, PORTA DD 0.4 0 MC9S08QD4 Series MCU Data Sheet, Rev. 6 and could result DD 125 105 –40 2.4 2.8 vs 125 105 –40 1.2 1.4 –1.6 vs Freescale Semiconductor ...
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... Figure A-3. Typical Low-Side Driver (Sink) Characteristics High Drive (PTxDSn = 1 0.2 Figure A-4. Typical Low-Side Driver (Sink) Characteristics High Drive (PTxDSn = 1), V Freescale Semiconductor Typical Low-side Driver (HDS) Characteristics 5.0 V, PORTA DD 0.8 1.2 1 Typical Low-side Driver (HDS) Characteristics ...
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... Figure A-6. Typical High-Side Driver (Source) Characteristics Low Drive (PTxDSn = 0), V 180 Typical High-side Driver (LDS) Characteristics 5.0 V, PORTA DD 3.2 3 3.0 V, PORTA DD 1.8 2 2.2 2 MC9S08QD4 Series MCU Data Sheet, Rev. 6 125 105 –40 4.8 5.2 vs 125 105 –40 2 Freescale Semiconductor ...
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... Figure A-7. Typical High-Side Driver (Source) Characteristics High Drive (PTxDSn = 1 –2 –4 –6 –8 –10 –12 1.6 Figure A-8. Typical High-Side Driver (Source) Characteristics High Drive (PTxDSn = 1), V Freescale Semiconductor Typical High-side Driver (HDS) Characteristics 5.0 V, PORTA DD 4 2.8 3.2 3.6 4 ...
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... Typical Max 4 5 0.95 1.5 3 0. 1.55 2.2 3 1.50 2.2 5 0. 0.80 7 0. 0.80 7 0. 0.90 7 0. 0.90 7 400 3 350 5 110 Freescale Semiconductor Unit μA μA μA μA μA μA μA μ μA μA μA μA ...
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... Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. Wait mode typical is 560 μ with f 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 Figure A-9. Typical Run I Freescale Semiconductor = 1 MHz. Bus Typical R (V =5.0 V, ADC off) vs. Bus Freq. IDD Bus/MHz vs. Bus Freq. (FEI) (ADC off) DD MC9S08QD4 Series MCU Data Sheet, Rev ...
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... Jitter percentage for Jitter Freescale Semiconductor Unit kHz kHz MHz MHz %f dco %f dco ms %f dco . BUS ...
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... Figure A-10. Typical Deviation of DCO Output vs. Temperature 0.20% 0.15% 0.10% 0.05% 0.00% –0.05% –0.10% –0.15% –0.20% 2.5 Figure A-11. Typical Deviation of DCO Output vs. Operating Voltage Freescale Semiconductor Deviation of DCO Output from Trimmed Frequency (8 MHz, 5 Temp. /C Deviation of DCO Output from Trimmed Frequency (8 MHz, 25 ° ...
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... MC9S08QD4 Series MCU Data Sheet, Rev Min Typical Max 1 — 8 — 700 1300 100 — — 100 — — 1.5 t cyc 100 — — 1.5 t cyc — 3 — — 30 — 500 — — 100 — — after V MSH Freescale Semiconductor Unit MHz μ μs DD ...
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... Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width TCLK TPMCHn TPMCHn Freescale Semiconductor t IHIL t ILIH Figure A-13. IRQ/KBIPx Timing Table A-9. TPM/MTIM Input Timing Symbol f TCLK ...
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... V V REFH Not Tested 5 15 kΩ Not Tested External to (2) — 10 kΩ MCU 4.883 5.371 V REFH mV 19.53 21.48 ±1.5 ±3.5 Includes LSB ±0.7 ±1.0 quantization ±0.5 ±1.0 LSB ±0.3 ±0.5 ±0.5 ±1.0 LSB ±0.3 ±0.5 Freescale Semiconductor = Bus N /2 ...
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... Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. ...
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... Appendix A Electrical Characteristics 190 MC9S08QD4 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor ...
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... Figure 12-7. Numbering Scheme for Consumer and Industrial Products • Numbering Scheme for Automotive Products Status (S = Fully Qualified) Memory (9 = Flash-based) Core Family Figure B-1. Numbering Scheme for Automotive Products Freescale Semiconductor Table B-1. Device Numbering System Memory Available Packages RAM 4 KB 256 128 SOIC ...
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... The following pages are mechanical specifications for the package options. See document number of each package type. Pin Count 8 8 192 Table B-2. Package Information Type Designator PDIP PC NB SOIC SC MC9S08QD4 Series MCU Data Sheet, Rev. 6 Table B-2 for the Document No. 98ASB42420B 98ASB42564B Freescale Semiconductor ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...