MC9S08QD2CSC Freescale, MC9S08QD2CSC Datasheet - Page 151
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MC9S08QD2CSC
Manufacturer Part Number
MC9S08QD2CSC
Description
Manufacturer
Freescale
Datasheet
1.MC9S08QD2CSC.pdf
(198 pages)
Specifications of MC9S08QD2CSC
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
128Byte
# I/os (max)
4
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
4-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC N
Program Memory Type
Flash
Program Memory Size
2KB
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S08QD2CSC
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MC9S08QD2CSCR
Manufacturer:
FREESCALE
Quantity:
310
11.3.4
TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the
interrupt enable, channel configuration, and pin function.
Freescale Semiconductor
ELSn[B:A]
Reset
CHnIE
CHnF
MSnB
MSnA
Field
3:2
7
6
5
4
W
R
CHnF
Timer Channel n Status and Control Register (TPMxCnSC)
Channel n Flag — When channel n is configured for input capture, this flag bit is set when an active edge occurs
on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when
the value in the TPM counter registers matches the value in the TPM channel n value registers. This flag is
seldom used with center-aligned PWMs because it is set every time the counter matches the channel value
register, which correspond to both edges of the active duty cycle period.
A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF
by reading TPMxCnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt request occurs before
the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence
was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a
previous CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect.
0 No input capture or output compare event occurred on channel n
1 Input capture or output compare event occurred on channel n
Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE.
0 Channel n interrupt requests disabled (use software polling)
1 Channel n interrupt requests enabled
Mode Select B for TPM Channel n — When CPWMS = 0, MSnB = 1 configures TPM channel n for
edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to
Mode Select A for TPM Channel n — When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for
input capture mode or output compare mode. Refer to
controls.
Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by
CPWMS:MSnB:MSnA and shown in
input capture event, select the level that will be driven in response to an output compare match, or select the
polarity of the PWM output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer
channel functions. This function is typically used to temporarily disable an input capture channel or to make the
timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer
that does not require the use of a pin.
0
7
Figure 11-8. Timer Channel n Status and Control Register (TPMxCnSC)
= Unimplemented or Reserved
CHnIE
0
6
Table 11-4. TPMxCnSC Register Field Descriptions
MC9S08QD4 Series MCU Data Sheet, Rev. 6
MSnB
0
5
Table
MSnA
11-5, these bits select the polarity of the input edge that triggers an
0
4
Description
Table 11-5
ELSnB
3
0
for a summary of channel mode and setup
Timer/Pulse-Width Modulator (S08TPMV2)
ELSnA
0
2
Table
0
0
1
11-5.
0
0
0
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