MC9S08QD2CSC Freescale, MC9S08QD2CSC Datasheet - Page 51
MC9S08QD2CSC
Manufacturer Part Number
MC9S08QD2CSC
Description
Manufacturer
Freescale
Datasheet
1.MC9S08QD2CSC.pdf
(198 pages)
Specifications of MC9S08QD2CSC
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
128Byte
# I/os (max)
4
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
4-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC N
Program Memory Type
Flash
Program Memory Size
2KB
Lead Free Status / RoHS Status
Compliant
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Quantity
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Part Number:
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Quantity:
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Chapter 5
Resets, Interrupts, and General System Control
5.1
This chapter discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts
in the MC9S08QD4 series. Some interrupt sources from peripheral modules are discussed in greater detail
within other sections of this data sheet. This section gathers basic information about all reset and interrupt
sources in one place for easy reference. A few reset and interrupt sources, including the computer
operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral
systems with their own chapters but are part of the system control logic.
5.2
Reset and interrupt features include:
5.3
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially
configured as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the
condition code register (CCR) is set to block maskable interrupts so the user program has a chance to
initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset.
The MC9S08QD4 series has the following sources for reset:
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register.
Freescale Semiconductor
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Multiple sources of reset for flexible system configuration and reliable operation
Reset status register (SRS) to indicate source of most recent reset
Separate interrupt vectors for each module (reduces polling overhead) (see
External pin reset (PIN) - enabled using RSTPE in SOPT1
Power-on reset (POR)
Low-voltage detect (LVD)
Computer operating properly (COP) timer
Illegal opcode detect (ILOP)
Illegal address detect (ILAD)
Background debug forced reset
Introduction
Features
MCU Reset
MC9S08QD4 Series MCU Data Sheet, Rev. 6
Table
5-2)
51
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