MC9S08QD2CSC Freescale, MC9S08QD2CSC Datasheet - Page 64

• Manufacturer Part Number: MC9S08QD2CSC
• Manufacturer: Freescale

Specifications of MC9S08QD2CSC

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 4
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 4-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Program Memory Type: Flash
• Program Memory Size: 2KB
• Lead Free Status / RoHS Status: Compliant

1
2
Chapter 5 Resets, Interrupts, and General System Control
1
2
3
5.8.8
This high-page register contains status and control bits to support the low voltage detect function, and to
enable the bandgap voltage reference for use by the ADC module. To configure the low voltage detect trip
voltage, see
64
Bit 1 is a reserved bit that must always be written to 0.
This bit can be written only one time after reset. Additional writes are ignored.
Values are shown in this column based on t
value.
The initial RTI timeout period will be up to one 1 kHz clock period less than the time specified.
t
Reset:
LVDACK
ext
RTIS2:RTIS1:RTIS0
Field
LVDF
is the period of the 32 kHz ICS frequency.
7
6
W
R
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
LVDF
System Power Management Status and Control 1 Register
(SPMSC1)
Table 5-13
Figure 5-10. System Power Management Status and Control 1 Register (SPMSC1)
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
0
7
= Unimplemented or Reserved
LVDACK
for the LVDV bit description in SPMSC2.
0
0
6
Using Internal 1 kHz Clock Source
Table 5-12. SPMSC1 Register Field Descriptions
MC9S08QD4 Series MCU Data Sheet, Rev. 6
Table 5-11. Real-Time Interrupt Period
LVDIE
RTI
0
5
Disable RTI
128 ms
256 ms
512 ms
1.024 s
= 1 ms. See t
32 ms
64 ms
8 ms
LVDRE
1
4
RTI
2
Description
in the
1 2
Section A.8.1, “Control
LVDSE
3
1
Using 32 kHz ICS Clock Source
LVDE
1
2
2
Period = t
Timing,” for the tolerance of this
Disable RTI
t
t
t
t
t
t
ext
ext
t
ext
ext
ext
ext
ext
× 16384
× 32768
× 1024
× 2048
× 4096
× 8192
× 256
Freescale Semiconductor
1
0
0
ext
1
3
BGBE
0
0