MC9S08QD2CSC Freescale, MC9S08QD2CSC Datasheet - Page 59

• Manufacturer Part Number: MC9S08QD2CSC
• Manufacturer: Freescale

Specifications of MC9S08QD2CSC

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 4
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 4-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Program Memory Type: Flash
• Program Memory Size: 2KB
• Lead Free Status / RoHS Status: Compliant

1
5.8.2
This high-page register includes read-only status flags to indicate the source of the most recent reset. When
a debug host forces reset by writing 1 to BDFR in the SBDFR register, all of the status bits in SRS will be
cleared. Writing any value to this register address clears the COP watchdog timer without affecting the
contents of this register. The reset state of these bits depends on what caused the MCU to reset.
Freescale Semiconductor
Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits
corresponding to sources that are not active at the time of reset entry will be cleared.
IRQMOD
IRQACK
reset:
POR:
other
IRQIE
LVR:
Field
Field
POR
Any
PIN
2
1
0
7
6
W
R
System Reset Status Register (SRS)
POR
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt
request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF = 1.
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt
request events. See
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVR threshold.
0 Reset not caused by POR.
1 POR caused reset.
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
1
0
0
7
Table 5-3. IRQSC Register Field Descriptions (continued)
PIN
(1)
0
0
6
Section 5.5.2.2, “Edge and Level
Writing any value to SRS address clears COP watchdog timer.
Table 5-4. SRS Register Field Descriptions
MC9S08QD4 Series MCU Data Sheet, Rev. 6
Figure 5-3. System Reset Status (SRS)
COP
(1)
0
0
5
ILOP
(1)
0
0
4
Description
Description
Sensitivity,” for more details.
Chapter 5 Resets, Interrupts, and General System Control
ILAD
(1)
3
0
0
0
2
0
0
0
LVD
1
1
0
1
0
0
0
0
0
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