MC9S08QG8CDTER Freescale, MC9S08QG8CDTER Datasheet - Page 17

• Manufacturer Part Number: MC9S08QG8CDTER
• Manufacturer: Freescale

Specifications of MC9S08QG8CDTER

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Lead Free Status / RoHS Status: Compliant

Section Number
14.1 Introduction ................................................................................................................................... 191
14.2 Register Definition ........................................................................................................................ 197
14.3 Functional Description .................................................................................................................. 204
14.4 Additional SCI Functions.............................................................................................................. 208
15.1 Introduction ................................................................................................................................... 211
15.2 External Signal Description .......................................................................................................... 216
15.3 Modes of Operation....................................................................................................................... 217
15.4 Register Definition ........................................................................................................................ 217
Freescale Semiconductor
14.1.1 Features ............................................................................................................................194
14.1.2 Modes of Operation .........................................................................................................194
14.1.3 Block Diagram .................................................................................................................195
14.2.1 SCI Baud Rate Registers (SCIBDH, SCIBHL) ...............................................................197
14.2.2 SCI Control Register 1 (SCIC1) ......................................................................................198
14.2.3 SCI Control Register 2 (SCIC2) ......................................................................................199
14.2.4 SCI Status Register 1 (SCIS1) .........................................................................................200
14.2.5 SCI Status Register 2 (SCIS2) .........................................................................................202
14.2.6 SCI Control Register 3 (SCIC3) ......................................................................................202
14.2.7 SCI Data Register (SCID)................................................................................................203
14.3.1 Baud Rate Generation ......................................................................................................204
14.3.2 Transmitter Functional Description .................................................................................204
14.3.3 Receiver Functional Description .....................................................................................206
14.3.4 Interrupts and Status Flags...............................................................................................207
14.4.1 8- and 9-Bit Data Modes..................................................................................................208
14.4.2 Stop Mode Operation.......................................................................................................209
14.4.3 Loop Mode.......................................................................................................................209
14.4.4 Single-Wire Operation .....................................................................................................209
15.1.1 Features ............................................................................................................................213
15.1.2 Block Diagrams ...............................................................................................................213
15.1.3 SPI Baud Rate Generation ...............................................................................................215
15.2.1 SPSCK — SPI Serial Clock.............................................................................................216
15.2.2 MOSI — Master Data Out, Slave Data In .......................................................................216
15.2.3 MISO — Master Data In, Slave Data Out .......................................................................216
15.2.4 SS — Slave Select ...........................................................................................................216
15.3.1 SPI in Stop Modes ...........................................................................................................217
15.4.1 SPI Control Register 1 (SPIC1) .......................................................................................217
15.4.2 SPI Control Register 2 (SPIC2) .......................................................................................218
15.4.3 SPI Baud Rate Register (SPIBR).....................................................................................219
Serial Communications Interface (S08SCIV3)
Serial Peripheral Interface (S08SPIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Chapter 14
Chapter 15
Title
Page
15