MC9S08QG8CDTER Freescale, MC9S08QG8CDTER Datasheet - Page 233

• Manufacturer Part Number: MC9S08QG8CDTER
• Manufacturer: Freescale

Specifications of MC9S08QG8CDTER

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Lead Free Status / RoHS Status: Compliant

All TPM channels are programmable independently as input capture, output compare, or buffered
edge-aligned PWM channels.
16.2
When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled.
After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive
pullups disabled.
16.2.1
When control bits CLKSB:CLKSA in the timer status and control register are set to 1:1, the prescaler and
consequently the 16-bit counter for TPM are driven by an external clock source, TPMxCLK, connected to
an I/O pin. A synchronizer is needed between the external clock and the rest of the TPM. This synchronizer
is clocked by the bus clock so the frequency of the external source must be less than one-half the frequency
of the bus rate clock. The upper frequency limit for this external clock source is specified to be one-fourth
the bus frequency to conservatively accommodate duty cycle and phase-locked loop (PLL) or
frequency-locked loop (FLL) frequency jitter effects.
On some devices the external clock input is shared with one of the TPM channels. When a TPM channel
is shared as the external clock input, the associated TPM channel cannot use the pin. (The channel can still
be used in output compare mode as a software timer.) Also, if one of the TPM channels is used as the
external clock input, the corresponding ELSnB:ELSnA control bits must be set to 0:0 so the channel is not
trying to use the same pin.
16.2.2
Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the
configuration of the channel. In some cases, no pin function is needed so the pin reverts to being controlled
by general-purpose I/O controls. When a timer has control of a port pin, the port data and data direction
registers do not affect the related pin(s). See the
about shared pin functions.
16.3
The TPM includes:
Each timer channel has:
Refer to the direct-page register summary in the
assignments for all TPM registers. This section refers to registers and control bits only by their names. A
Freescale Semiconductor
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An 8-bit status and control register (TPMSC)
A 16-bit counter (TPMCNTH:TPMCNTL)
A 16-bit modulo register (TPMMODH:TPMMODL)
An 8-bit status and control register (TPMCnSC)
A 16-bit channel value register (TPMCnVH:TPMCnVL)
External Signal Description
Register Definition
External TPM Clock Sources
TPMCHn — TPM Channel n I/O Pins
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Memory
Pins and Connections
chapter of this data sheet for the absolute address
chapter for additional information
Timer/Pulse-Width Modulator (S08TPMV2)
231