PPC440GP-3FC400C Applied Micro Circuits Corporation, PPC440GP-3FC400C Datasheet - Page 11

• Manufacturer Part Number: PPC440GP-3FC400C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GP-3FC400C

• Family Name: 440GP
• Device Core: PowerPC
• Device Core Size: 32/64Bit
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9/1.95V
• Operating Supply Voltage (min): 1.65/1.7V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: FCBGA
• Lead Free Status / RoHS Status: Not Compliant

Revision 1.11 – August 27, 2010
DDR SDRAM Memory Controller
The Double Data Rate (DDR) SDRAM memory controller supports industry standard 184-pin DIMMs and other
discrete devices. Up to four 512MB logical banks are supported in limited configurations. Global memory timings,
address and bank sizes, and memory addressing modes are programmable.
Features include:
External Peripheral Bus Controller (EBC)
Features include:
AppliedMicro Proprietary
Data Sheet
• Supports initiation of transfer to the following address spaces:
• Registered and non-registered industry standard DIMMs and other discrete devices
• 32- or 64-bit memory interface with optional 8-bit ECC (SEC/DED)
• Sustainable 2.1GB/s peak bandwidth at 133MHz
• SSTL_2 logic
• 1 to 4 chip selects
• CAS latencies of 2, 2.5 and 3 supported
• PC200/266 support
• Page mode accesses (up to eight open pages) with configurable paging policy
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Power management (self-refresh, suspend, sleep)
• Up to eight ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
• Up to 66.66MHz operation (266MB/s)
• Burst and non-burst devices
• 8-, 16-, 32-bit byte-addressable data bus
• 32-bit address, 4GB address space
• Peripheral Device pacing with external “Ready”
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device
• Programmable address mapping
• External master interface
- Single beat I/O reads and writes
- Single beat and burst memory reads and writes
- Single beat configuration reads and writes (type 0 and type 1)
- Single beat special cycles
- 256 Wait States for non-burst
- 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
440GP – Power PC 440GP Embedded Processor
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